Lines Matching defs:blocks
2014 /* Special blocks iterator is currently used to configure security protection bits,
2015 * and read global errors. Most HW blocks are addressable and those who aren't (N/A)-
2028 /* Skip all PSOC blocks except for PSOC_GLOBAL_CONF */
2031 /* Skip all CPU blocks except for CPU_IF */
3084 /* Each ARC scheduler has 2 consecutive DCCM blocks */
3188 struct user_mapped_block *blocks = gaudi2->mapped_blocks;
3190 HL_USR_MAPPED_BLK_INIT(&blocks[start_idx++], mmDCORE0_DEC0_CMD_BASE, HL_BLOCK_SIZE);
3191 HL_USR_MAPPED_BLK_INIT(&blocks[start_idx++], mmDCORE0_DEC1_CMD_BASE, HL_BLOCK_SIZE);
3192 HL_USR_MAPPED_BLK_INIT(&blocks[start_idx++], mmDCORE1_DEC0_CMD_BASE, HL_BLOCK_SIZE);
3193 HL_USR_MAPPED_BLK_INIT(&blocks[start_idx++], mmDCORE1_DEC1_CMD_BASE, HL_BLOCK_SIZE);
3194 HL_USR_MAPPED_BLK_INIT(&blocks[start_idx++], mmDCORE2_DEC0_CMD_BASE, HL_BLOCK_SIZE);
3195 HL_USR_MAPPED_BLK_INIT(&blocks[start_idx++], mmDCORE2_DEC1_CMD_BASE, HL_BLOCK_SIZE);
3196 HL_USR_MAPPED_BLK_INIT(&blocks[start_idx++], mmDCORE3_DEC0_CMD_BASE, HL_BLOCK_SIZE);
3197 HL_USR_MAPPED_BLK_INIT(&blocks[start_idx++], mmDCORE3_DEC1_CMD_BASE, HL_BLOCK_SIZE);
3198 HL_USR_MAPPED_BLK_INIT(&blocks[start_idx++], mmPCIE_DEC0_CMD_BASE, HL_BLOCK_SIZE);
3199 HL_USR_MAPPED_BLK_INIT(&blocks[start_idx], mmPCIE_DEC1_CMD_BASE, HL_BLOCK_SIZE);
3205 struct user_mapped_block *blocks = gaudi2->mapped_blocks;
3215 blocks[i].address = gaudi2_arc_dccm_bases[i];
3216 blocks[i].size = block_size;
3219 blocks[NUM_ARC_CPUS].address = mmARC_FARM_ARC0_ACP_ENG_BASE;
3220 blocks[NUM_ARC_CPUS].size = HL_BLOCK_SIZE;
3222 blocks[NUM_ARC_CPUS + 1].address = mmARC_FARM_ARC1_ACP_ENG_BASE;
3223 blocks[NUM_ARC_CPUS + 1].size = HL_BLOCK_SIZE;
3225 blocks[NUM_ARC_CPUS + 2].address = mmARC_FARM_ARC2_ACP_ENG_BASE;
3226 blocks[NUM_ARC_CPUS + 2].size = HL_BLOCK_SIZE;
3228 blocks[NUM_ARC_CPUS + 3].address = mmARC_FARM_ARC3_ACP_ENG_BASE;
3229 blocks[NUM_ARC_CPUS + 3].size = HL_BLOCK_SIZE;
3231 blocks[NUM_ARC_CPUS + 4].address = mmDCORE0_MME_QM_ARC_ACP_ENG_BASE;
3232 blocks[NUM_ARC_CPUS + 4].size = HL_BLOCK_SIZE;
3234 blocks[NUM_ARC_CPUS + 5].address = mmDCORE1_MME_QM_ARC_ACP_ENG_BASE;
3235 blocks[NUM_ARC_CPUS + 5].size = HL_BLOCK_SIZE;
3237 blocks[NUM_ARC_CPUS + 6].address = mmDCORE2_MME_QM_ARC_ACP_ENG_BASE;
3238 blocks[NUM_ARC_CPUS + 6].size = HL_BLOCK_SIZE;
3240 blocks[NUM_ARC_CPUS + 7].address = mmDCORE3_MME_QM_ARC_ACP_ENG_BASE;
3241 blocks[NUM_ARC_CPUS + 7].size = HL_BLOCK_SIZE;
3251 blocks[umr_start_idx + i].address =
3256 blocks[umr_start_idx + i].size = HL_BLOCK_SIZE;
3263 blocks[USR_MAPPED_BLK_SM_START_IDX + 2 * (i - 1)].size = SM_OBJS_BLOCK_SIZE;
3264 blocks[USR_MAPPED_BLK_SM_START_IDX + 2 * (i - 1) + 1].size = HL_BLOCK_SIZE;
3266 blocks[USR_MAPPED_BLK_SM_START_IDX + 2 * (i - 1)].address =
3269 blocks[USR_MAPPED_BLK_SM_START_IDX + 2 * (i - 1) + 1].address =
3422 /* Configure Special blocks */
3434 /* Configure when to skip Special blocks */
8356 /* There is a single event per NIC macro, so should check its both QMAN blocks */
10288 for (i = 0 ; i < cfg_ctx->blocks ; i++)