Lines Matching defs:asid
5463 u32 stlb_base, u32 asid, u64 phys_addr)
5473 WREG32(stlb_base + STLB_ASID_OFFSET, asid);
5487 dev_err(hdev->dev, "Timeout during MMU hop0 config of asid %d\n", asid);
5688 u32 flags, u32 asid, u64 va, u64 size)
5701 asid << MMU_RANGE_INV_ASID_SHIFT);
5743 u32 asid, max_asid = prop->max_asid;
5750 for (asid = 0 ; asid < max_asid ; asid++) {
5751 hop0_addr = hdev->mmu_priv.hr.mmu_asid_hop0[asid].phys_addr;
5752 rc = gaudi2_mmu_update_asid_hop0_addr(hdev, stlb_base, asid, hop0_addr);
5754 dev_err(hdev->dev, "failed to set hop0 addr for asid %d\n", asid);
6730 bool mmu_bypass, u32 asid)
6734 rw_asid = (asid << ARC_FARM_KDMA_CTX_AXUSER_HB_ASID_RD_SHIFT) |
6735 (asid << ARC_FARM_KDMA_CTX_AXUSER_HB_ASID_WR_SHIFT);
7447 static void gaudi2_mmu_dcore_prepare(struct hl_device *hdev, int dcore_id, u32 asid)
7449 u32 rw_asid = (asid << ARC_FARM_KDMA_CTX_AXUSER_HB_ASID_RD_SHIFT) |
7450 (asid << ARC_FARM_KDMA_CTX_AXUSER_HB_ASID_WR_SHIFT);
7473 WREG32(mmDCORE0_SYNC_MNGR_GLBL_ASID_NONE_SEC_PRIV + dcore_offset, asid);
7479 reg_val = (asid << DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_ASID_RD_SHIFT) |
7480 (asid << DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_ASID_WR_SHIFT);
7546 static void gaudi2_arc_mmu_prepare(struct hl_device *hdev, u32 cpu_id, u32 asid)
7552 /* Enable MMU and configure asid for all relevant ARC regions */
7554 reg_val |= FIELD_PREP(ARC_FARM_ARC0_AUX_ARC_REGION_CFG_0_ASID_MASK, asid);
7590 static int gaudi2_arc_mmu_prepare_all(struct hl_device *hdev, u32 asid)
7595 return hl_fw_cpucp_engine_core_asid_set(hdev, asid);
7598 gaudi2_arc_mmu_prepare(hdev, i, asid);
7604 gaudi2_arc_mmu_prepare(hdev, gaudi2_queue_id_to_arc_id[i], asid);
7610 static int gaudi2_mmu_shared_prepare(struct hl_device *hdev, u32 asid)
7616 rw_asid = FIELD_PREP(ARC_FARM_KDMA_CTX_AXUSER_HB_ASID_RD_MASK, asid) |
7617 FIELD_PREP(ARC_FARM_KDMA_CTX_AXUSER_HB_ASID_WR_MASK, asid);
7634 RMWREG32(mmROT0_CPL_QUEUE_AWUSER + offset, asid, MMUBP_ASID_MASK);
7635 RMWREG32(mmROT0_DESC_HBW_ARUSER_LO + offset, asid, MMUBP_ASID_MASK);
7636 RMWREG32(mmROT0_DESC_HBW_AWUSER_LO + offset, asid, MMUBP_ASID_MASK);
7650 rc = gaudi2_arc_mmu_prepare_all(hdev, asid);
7669 static int gaudi2_mmu_prepare(struct hl_device *hdev, u32 asid)
7679 if (asid & ~DCORE0_HMMU0_STLB_ASID_ASID_MASK) {
7680 dev_crit(hdev->dev, "asid %u is too big\n", asid);
7687 rc = gaudi2_mmu_shared_prepare(hdev, asid);
7692 tpc_mmu_data.rw_asid = (asid << ARC_FARM_KDMA_CTX_AXUSER_HB_ASID_RD_SHIFT) |
7693 (asid << ARC_FARM_KDMA_CTX_AXUSER_HB_ASID_WR_SHIFT);
7696 gaudi2_mmu_dcore_prepare(hdev, i, asid);
10253 static int gaudi2_context_switch(struct hl_device *hdev, u32 asid)
10342 ctx->asid, reserved_va_base, SZ_2M);
10351 gaudi2_kdma_set_mmbp_asid(hdev, false, ctx->asid);
10384 ctx->asid, reserved_va_base, SZ_2M);
10526 rc = gaudi2_mmu_prepare(ctx->hdev, ctx->asid);
10551 if (ctx->asid == HL_KERNEL_ASID_ID)