Lines Matching defs:address
112 /* HBM MMU address scrambling parameters */
967 {"payload address of monitor is not aligned to 4B", "monitor addr"},
2248 * 1. partition the virtual address space to DRAM-page (whole) pages.
2250 * 2. limit the amount of virtual address space we got from 1 above to
2251 * a multiple of 64M as we don't want the scrambled address to cross
2252 * the DRAM virtual address space.
2254 * 3. determine the and address accordingly
2257 * the DRAM address MSBs (63:48) are not part of the roundup calculation
2524 * fetch BAR physical base address
2528 /* Base address must be aligned to Bar size which is 256 MB */
2534 /* Fetch physical BAR address */
3072 /* Fetch ARC scratchpad address */
3215 blocks[i].address = gaudi2_arc_dccm_bases[i];
3219 blocks[NUM_ARC_CPUS].address = mmARC_FARM_ARC0_ACP_ENG_BASE;
3222 blocks[NUM_ARC_CPUS + 1].address = mmARC_FARM_ARC1_ACP_ENG_BASE;
3225 blocks[NUM_ARC_CPUS + 2].address = mmARC_FARM_ARC2_ACP_ENG_BASE;
3228 blocks[NUM_ARC_CPUS + 3].address = mmARC_FARM_ARC3_ACP_ENG_BASE;
3231 blocks[NUM_ARC_CPUS + 4].address = mmDCORE0_MME_QM_ARC_ACP_ENG_BASE;
3234 blocks[NUM_ARC_CPUS + 5].address = mmDCORE1_MME_QM_ARC_ACP_ENG_BASE;
3237 blocks[NUM_ARC_CPUS + 6].address = mmDCORE2_MME_QM_ARC_ACP_ENG_BASE;
3240 blocks[NUM_ARC_CPUS + 7].address = mmDCORE3_MME_QM_ARC_ACP_ENG_BASE;
3251 blocks[umr_start_idx + i].address =
3266 blocks[USR_MAPPED_BLK_SM_START_IDX + 2 * (i - 1)].address =
3269 blocks[USR_MAPPED_BLK_SM_START_IDX + 2 * (i - 1) + 1].address =
5122 * Some initiators cannot have HBW address in their completion address registers, and thus cannot
5583 * Note: that the start address we set in register, is not included in
5585 * that's why we need to set lower address than the one we actually
5706 /* As range invalidation does not support zero address we will
5955 * a different address, there will be an error
5962 * base address of dram
5965 dev_err(hdev->dev, "failed to map HBM bar to DRAM base address\n");
6654 /* Just check if CB address is valid */
6695 dev_err(hdev->dev, "CB address %p + 0x%x for internal QMAN is not valid\n",
6756 /* Configure this address with CQ_ID 0 because CQ_EN is set */
6759 /* Configure this address with CS index because CQ_EN is set */
7750 "ECC error detected. address: %#llx. Syndrom: %#llx. block id %u. critical %u.",
7861 "%s-RAZWI SHARED RR HBW %s error, address %#llx, Initiator coordinates 0x%x\n",
7886 "%s-RAZWI SHARED RR LBW %s error, mstr_if 0x%llx, captured address 0x%llX Initiator coordinates 0x%x\n",
8195 "PSOC HBW AW RAZWI: %s, address (aligned to 128 byte): 0x%llX\n",
8209 "PSOC HBW AR RAZWI: %s, address (aligned to 128 byte): 0x%llX\n",
8221 "PSOC LBW AW RAZWI: %s, address (aligned to 128 byte): 0x%X\n",
8233 "PSOC LBW AR RAZWI: %s, address (aligned to 128 byte): 0x%X\n",
8253 /* PSOC RAZWI interrupt occurs only when trying to access a bad address */
9117 "READ ERROR address: sid(%u), bg(%u), ba(%u), col(%u), row(%u)\n",
9998 * set QM as trusted to allow it to access physical address with MMU bp.
10088 dev_err(hdev->dev, "Failed to scrub dram, address: 0x%llx size: %llu\n",
10698 * monitor_base should be the content of the base0 address registers,
10703 /* First monitor config packet: low address of the sync */
10709 /* Second monitor config packet: high address of the sync */
10771 * hl_mmu_scramble - converts a dram (non power of 2) page-size aligned address
10772 * to DMMU page-size address (64MB) before mapping it in
10781 * Phys address in MMU last
10794 /* accept any address in the DRAM address space */
10814 /* accept any address in the DRAM address space */
10859 if (block_addr == CFG_BASE + gaudi2->mapped_blocks[i].address) {
10867 dev_err(hdev->dev, "Invalid block address %#llx", block_addr);
10877 u64 address;
10891 offset_in_bar = CFG_BASE + gaudi2->mapped_blocks[block_id].address - STM_FLASH_BASE_ADDR;
10893 address = pci_resource_start(hdev->pdev, SRAM_CFG_BAR_ID) + offset_in_bar;
10898 rc = remap_pfn_range(vma, vma->vm_start, address >> PAGE_SHIFT,
11119 * this mismatch when calculating the address to place in the MMU page table.