Lines Matching refs:dma_offset
2640 u32 dma_offset = dma_id * DMA_CORE_OFFSET;
2644 WREG32(mmDMA0_CORE_RD_MAX_OUTSTAND + dma_offset, 0);
2645 WREG32(mmDMA0_CORE_RD_MAX_SIZE + dma_offset, 0);
2648 WREG32(mmDMA0_CORE_LBW_MAX_OUTSTAND + dma_offset, 15);
2654 WREG32(mmDMA0_CORE_ERR_CFG + dma_offset, dma_err_cfg);
2660 WREG32(mmDMA0_CORE_ERRMSG_ADDR_LO + dma_offset,
2662 WREG32(mmDMA0_CORE_ERRMSG_ADDR_HI + dma_offset,
2665 WREG32(mmDMA0_CORE_ERRMSG_WDATA + dma_offset,
2667 WREG32(mmDMA0_CORE_PROT + dma_offset,
2670 WREG32(mmDMA0_CORE_SECURE_PROPS + dma_offset,
2672 WREG32(mmDMA0_CORE_CFG_0 + dma_offset, 1 << DMA0_CORE_CFG_0_EN_SHIFT);
4567 u32 dma_offset = dma_id * DMA_CORE_OFFSET;
4576 WREG32(mmDMA0_CORE_SRC_BASE_LO + dma_offset,
4578 WREG32(mmDMA0_CORE_SRC_BASE_HI + dma_offset,
4580 WREG32(mmDMA0_CORE_DST_BASE_LO + dma_offset,
4582 WREG32(mmDMA0_CORE_DST_BASE_HI + dma_offset,
4584 WREG32(mmDMA0_CORE_DST_TSIZE_0 + dma_offset,
4586 WREG32(mmDMA0_CORE_COMMIT + dma_offset,
4597 u32 dma_offset = dma_id * DMA_CORE_OFFSET;
4601 mmDMA0_CORE_STS0 + dma_offset,
5795 u32 dma_offset = i * DMA_CORE_OFFSET;
5797 WREG32(mmDMA0_CORE_WR_COMP_ADDR_LO + dma_offset,
5799 WREG32(mmDMA0_CORE_WR_COMP_ADDR_HI + dma_offset,
5801 WREG32(mmDMA0_CORE_WR_COMP_WDATA + dma_offset, 0x80000001);
5807 WREG32(mmDMA0_CORE_WR_AWUSER_31_11 + dma_offset,
5880 u64 dma_offset;
5883 dma_offset = dma_id * DMA_CORE_OFFSET;
5885 WREG32(mmDMA0_CORE_SRC_BASE_LO + dma_offset, lower_32_bits(addr));
5886 WREG32(mmDMA0_CORE_SRC_BASE_HI + dma_offset, upper_32_bits(addr));
5887 WREG32(mmDMA0_CORE_DST_BASE_LO + dma_offset, lower_32_bits(dma_addr));
5888 WREG32(mmDMA0_CORE_DST_BASE_HI + dma_offset, upper_32_bits(dma_addr));
5889 WREG32(mmDMA0_CORE_DST_TSIZE_0 + dma_offset, size_to_dma);
5890 WREG32(mmDMA0_CORE_COMMIT + dma_offset,
5895 mmDMA0_CORE_STS0 + dma_offset,
5909 err_cause = RREG32(mmDMA0_CORE_ERR_CAUSE + dma_offset);
5915 WREG32(mmDMA0_CORE_ERR_CAUSE + dma_offset, err_cause);
5928 u64 dma_offset, qm_offset;
5942 dma_offset = dma_id * DMA_CORE_OFFSET;
5944 dma_core_sts0 = RREG32(mmDMA0_CORE_STS0 + dma_offset);
5952 dma_offset = dma_id * DMA_CORE_OFFSET;
5954 dma_core_sts0 = RREG32(mmDMA0_CORE_STS0 + dma_offset);
5976 WREG32_OR(mmDMA0_CORE_PROT + dma_offset, BIT(DMA0_CORE_PROT_VAL_SHIFT));
5979 err_cause = RREG32(mmDMA0_CORE_ERR_CAUSE + dma_offset);
5984 WREG32(mmDMA0_CORE_ERR_CAUSE + dma_offset, err_cause);
6015 WREG32_AND(mmDMA0_CORE_PROT + dma_offset,
6355 u32 tmp, timeout, dma_offset;
6383 dma_offset = gaudi_dma_assignment[GAUDI_PCI_DMA_1] * DMA_CORE_OFFSET;
6385 WREG32(mmDMA0_CORE_PROT + dma_offset,
6407 WREG32(mmDMA0_CORE_PROT + dma_offset, BIT(DMA0_CORE_PROT_ERR_VAL_SHIFT));
6433 u32 dma_id[2], dma_offset, err_cause[2], mask, i;
6464 dma_offset = dma_id[i] * DMA_CORE_OFFSET;
6465 err_cause[i] = RREG32(mmDMA0_CORE_ERR_CAUSE + dma_offset);