Lines Matching refs:dma_id
2544 static void gaudi_init_pci_dma_qman(struct hl_device *hdev, int dma_id,
2554 dma_qm_offset = dma_id * DMA_QMAN_OFFSET;
2620 dma_id);
2635 static void gaudi_init_dma_core(struct hl_device *hdev, int dma_id)
2640 u32 dma_offset = dma_id * DMA_CORE_OFFSET;
2666 gaudi_irq_map_table[GAUDI_EVENT_DMA0_CORE].cpu_id + dma_id);
2675 static void gaudi_enable_qman(struct hl_device *hdev, int dma_id,
2678 u32 dma_qm_offset = dma_id * DMA_QMAN_OFFSET;
2687 int i, j, dma_id, cpu_skip, nic_skip, cq_id = 0, q_idx, msi_vec = 0;
2693 dma_id = gaudi_dma_assignment[i];
2699 if (dma_id > 1) {
2708 q_idx = 4 * dma_id + j + cpu_skip;
2712 gaudi_init_pci_dma_qman(hdev, dma_id, j,
2716 gaudi_init_dma_core(hdev, dma_id);
2718 gaudi_enable_qman(hdev, dma_id, PCI_DMA_QMAN_ENABLE);
2724 static void gaudi_init_hbm_dma_qman(struct hl_device *hdev, int dma_id,
2734 dma_qm_offset = dma_id * DMA_QMAN_OFFSET;
2798 dma_id);
2817 if (gaudi_dma_assignment[dma_id] == GAUDI_ENGINE_ID_DMA_5) {
2834 int i, j, dma_id, internal_q_index;
2840 dma_id = gaudi_dma_assignment[GAUDI_HBM_DMA_1 + i];
2847 internal_q_index = dma_id * QMAN_STREAMS + j + 1;
2851 gaudi_init_hbm_dma_qman(hdev, dma_id, j,
2856 gaudi_init_hbm_dma_qman(hdev, dma_id, 4, 0);
2858 gaudi_init_dma_core(hdev, dma_id);
2860 gaudi_enable_qman(hdev, dma_id, HBM_DMA_QMAN_ENABLE);
4191 int dma_id;
4195 dma_id = gaudi_dma_assignment[GAUDI_PCI_DMA_1];
4196 dma_qm_offset = dma_id * DMA_QMAN_OFFSET;
4202 dma_id = gaudi_dma_assignment[GAUDI_PCI_DMA_2];
4203 dma_qm_offset = dma_id * DMA_QMAN_OFFSET;
4209 dma_id = gaudi_dma_assignment[GAUDI_HBM_DMA_1];
4210 dma_qm_offset = dma_id * DMA_QMAN_OFFSET;
4216 dma_id = gaudi_dma_assignment[GAUDI_HBM_DMA_2];
4217 dma_qm_offset = dma_id * DMA_QMAN_OFFSET;
4223 dma_id = gaudi_dma_assignment[GAUDI_HBM_DMA_3];
4224 dma_qm_offset = dma_id * DMA_QMAN_OFFSET;
4230 dma_id = gaudi_dma_assignment[GAUDI_HBM_DMA_4];
4231 dma_qm_offset = dma_id * DMA_QMAN_OFFSET;
4237 dma_id = gaudi_dma_assignment[GAUDI_HBM_DMA_5];
4238 dma_qm_offset = dma_id * DMA_QMAN_OFFSET;
4244 dma_id = gaudi_dma_assignment[GAUDI_HBM_DMA_6];
4245 dma_qm_offset = dma_id * DMA_QMAN_OFFSET;
4563 int rc, dma_id;
4566 for (dma_id = 0 ; dma_id < DMA_NUMBER_OF_CHANNELS ; dma_id++) {
4567 u32 dma_offset = dma_id * DMA_CORE_OFFSET;
4596 for (dma_id = 0 ; dma_id < DMA_NUMBER_OF_CHANNELS ; dma_id++) {
4597 u32 dma_offset = dma_id * DMA_CORE_OFFSET;
4610 dma_id);
5876 static int gaudi_dma_core_transfer(struct hl_device *hdev, int dma_id, u64 addr,
5883 dma_offset = dma_id * DMA_CORE_OFFSET;
5904 dma_id, addr);
5932 int rc = 0, dma_id;
5941 dma_id = gaudi_dma_assignment[GAUDI_PCI_DMA_1];
5942 dma_offset = dma_id * DMA_CORE_OFFSET;
5943 qm_offset = dma_id * DMA_QMAN_OFFSET;
5951 dma_id = gaudi_dma_assignment[GAUDI_PCI_DMA_2];
5952 dma_offset = dma_id * DMA_CORE_OFFSET;
5953 qm_offset = dma_id * DMA_QMAN_OFFSET;
5996 rc = gaudi_dma_core_transfer(hdev, dma_id, addr, size_to_dma,
6433 u32 dma_id[2], dma_offset, err_cause[2], mask, i;
6441 dma_id[0] = 0;
6442 dma_id[1] = 2;
6446 dma_id[0] = 1;
6447 dma_id[1] = 3;
6451 dma_id[0] = 4;
6452 dma_id[1] = 6;
6456 dma_id[0] = 5;
6457 dma_id[1] = 7;
6464 dma_offset = dma_id[i] * DMA_CORE_OFFSET;
8024 int i, dma_id, port;
8032 dma_id = gaudi_dma_assignment[i];
8033 offset = dma_id * DMA_QMAN_OFFSET;
8043 set_bit(GAUDI_ENGINE_ID_DMA_0 + dma_id, mask);
8045 hl_engine_data_sprintf(e, fmt, dma_id,