Lines Matching refs:asic_prop
516 struct asic_fixed_properties *prop = &hdev->asic_prop;
533 struct asic_fixed_properties *prop = &hdev->asic_prop;
733 if (hdev->asic_prop.iatu_done_by_fw)
758 if (hdev->asic_prop.iatu_done_by_fw)
801 struct asic_fixed_properties *prop = &hdev->asic_prop;
836 if (hdev->asic_prop.fw_security_enabled) {
837 hdev->asic_prop.iatu_done_by_fw = true;
843 hdev->asic_prop.gic_interrupts_enable = false;
855 hdev->asic_prop.iatu_done_by_fw = true;
887 kfree(hdev->asic_prop.hw_queues_props);
893 kfree(hdev->asic_prop.hw_queues_props);
908 struct asic_fixed_properties *prop = &hdev->asic_prop;
965 struct asic_fixed_properties *prop = &hdev->asic_prop;
1172 sob_id = hdev->asic_prop.collective_first_sob;
1462 hw_queue_prop = &hdev->asic_prop.hw_queues_props[queue_id];
1534 hw_queue_prop = &hdev->asic_prop.hw_queues_props[wait_queue_id];
1735 if (!hdev->asic_prop.fw_security_enabled)
1808 struct asic_fixed_properties *prop = &hdev->asic_prop;
1832 region->region_size = hdev->asic_prop.dram_size;
1930 if (!hdev->asic_prop.fw_security_enabled)
1950 if (!hdev->asic_prop.fw_security_enabled)
1972 for (i = 0 ; i < hdev->asic_prop.completion_queues_count ; i++)
2071 if (hdev->asic_prop.fw_security_enabled)
2074 if (hdev->asic_prop.fw_app_cpu_boot_dev_sts0 &
2139 if (hdev->asic_prop.fw_security_enabled)
2142 if (hdev->asic_prop.fw_bootfit_cpu_boot_dev_sts0 &
2205 if (hdev->asic_prop.fw_security_enabled)
2208 if (hdev->asic_prop.fw_bootfit_cpu_boot_dev_sts0 &
2457 if (hdev->asic_prop.fw_security_enabled)
2460 if (hdev->asic_prop.fw_bootfit_cpu_boot_dev_sts0 &
2601 irq_handler_offset = hdev->asic_prop.gic_interrupts_enable ?
2656 irq_handler_offset = hdev->asic_prop.gic_interrupts_enable ?
2772 irq_handler_offset = hdev->asic_prop.gic_interrupts_enable ?
2905 irq_handler_offset = hdev->asic_prop.gic_interrupts_enable ?
3041 irq_handler_offset = hdev->asic_prop.gic_interrupts_enable ?
3198 irq_handler_offset = hdev->asic_prop.gic_interrupts_enable ?
3558 if (hdev->asic_prop.fw_security_enabled)
3641 struct asic_fixed_properties *prop = &hdev->asic_prop;
3766 struct asic_fixed_properties *prop = &hdev->asic_prop;
3800 if (!hdev->asic_prop.fw_security_enabled)
3817 struct asic_fixed_properties *prop = &hdev->asic_prop;
3891 if (!hdev->asic_prop.fw_security_enabled) {
3925 if (hdev->asic_prop.iatu_done_by_fw)
4031 driver_performs_reset = !!(!hdev->asic_prop.fw_security_enabled &&
4032 !hdev->asic_prop.hard_reset_done_by_fw);
4046 irq_handler_offset = hdev->asic_prop.gic_interrupts_enable ?
4065 if (hdev->asic_prop.hard_reset_done_by_fw)
4071 if (hdev->asic_prop.hard_reset_done_by_fw)
4517 irq_handler_offset = hdev->asic_prop.gic_interrupts_enable ?
4560 struct asic_fixed_properties *prop = &hdev->asic_prop;
4621 struct asic_fixed_properties *prop = &hdev->asic_prop;
4791 for (i = 0 ; i < hdev->asic_prop.max_queues ; i++) {
4792 if (hdev->asic_prop.hw_queues_props[i].type == QUEUE_TYPE_EXT) {
5471 struct asic_fixed_properties *asic_prop = &hdev->asic_prop;
5489 asic_prop->sram_user_base_address,
5490 asic_prop->sram_end_address))
5495 asic_prop->dram_user_base_address,
5496 asic_prop->dram_end_address))
5502 asic_prop->pmmu.start_addr,
5503 asic_prop->pmmu.end_addr))
5860 u32 size = hdev->asic_prop.mmu_pgt_size +
5861 hdev->asic_prop.mmu_cache_mng_size;
5863 u64 addr = hdev->asic_prop.mmu_pgt_addr;
7046 if (hdev->asic_prop.fw_security_enabled) {
7342 if (hdev->asic_prop.fw_app_cpu_boot_dev_sts0 &
7375 if (hdev->asic_prop.fw_security_enabled) {
7862 if (hdev->asic_prop.fw_security_enabled && !reset_direct) {
7990 struct asic_fixed_properties *prop = &hdev->asic_prop;
8006 hdev->card_type = le32_to_cpu(hdev->asic_prop.cpucp_info.card_type);
8788 u32 irq_handler_offset = hdev->asic_prop.gic_interrupts_enable ?
9094 cpucp_info = &hdev->asic_prop.cpucp_info;