Lines Matching refs:CFG_BASE
572 prop->cfg_base_address = CFG_BASE;
661 prop->pcie_aux_dbi_reg_addr = CFG_BASE + mmPCIE_AUX_DBI;
718 (CFG_BASE - SPI_FLASH_BASE_ADDR);
847 rc = hl_pci_elbi_read(hdev, CFG_BASE + mmCPU_BOOT_DEV_STS0,
1813 region->region_base = CFG_BASE;
1815 region->offset_in_bar = CFG_BASE - SPI_FLASH_BASE_ADDR;
2556 mtr_base_en_lo = lower_32_bits(CFG_BASE +
2558 mtr_base_en_hi = upper_32_bits(CFG_BASE +
2560 so_base_en_lo = lower_32_bits(CFG_BASE +
2562 so_base_en_hi = upper_32_bits(CFG_BASE +
2564 mtr_base_ws_lo = lower_32_bits(CFG_BASE +
2566 mtr_base_ws_hi = upper_32_bits(CFG_BASE +
2568 so_base_ws_lo = lower_32_bits(CFG_BASE +
2570 so_base_ws_hi = upper_32_bits(CFG_BASE +
2614 lower_32_bits(CFG_BASE + irq_handler_offset));
2616 upper_32_bits(CFG_BASE + irq_handler_offset));
2661 lower_32_bits(CFG_BASE + irq_handler_offset));
2663 upper_32_bits(CFG_BASE + irq_handler_offset));
2736 mtr_base_en_lo = lower_32_bits(CFG_BASE +
2738 mtr_base_en_hi = upper_32_bits(CFG_BASE +
2740 so_base_en_lo = lower_32_bits(CFG_BASE +
2742 so_base_en_hi = upper_32_bits(CFG_BASE +
2744 mtr_base_ws_lo = lower_32_bits(CFG_BASE +
2746 mtr_base_ws_hi = upper_32_bits(CFG_BASE +
2748 so_base_ws_lo = lower_32_bits(CFG_BASE +
2750 so_base_ws_hi = upper_32_bits(CFG_BASE +
2792 lower_32_bits(CFG_BASE + irq_handler_offset));
2794 upper_32_bits(CFG_BASE + irq_handler_offset));
2877 mtr_base_lo = lower_32_bits(CFG_BASE +
2879 mtr_base_hi = upper_32_bits(CFG_BASE +
2881 so_base_lo = lower_32_bits(CFG_BASE +
2883 so_base_hi = upper_32_bits(CFG_BASE +
2928 lower_32_bits(CFG_BASE + irq_handler_offset));
2930 upper_32_bits(CFG_BASE + irq_handler_offset));
3002 mtr_base_en_lo = lower_32_bits(CFG_BASE +
3004 mtr_base_en_hi = upper_32_bits(CFG_BASE +
3006 so_base_en_lo = lower_32_bits(CFG_BASE +
3008 so_base_en_hi = upper_32_bits(CFG_BASE +
3010 mtr_base_ws_lo = lower_32_bits(CFG_BASE +
3012 mtr_base_ws_hi = upper_32_bits(CFG_BASE +
3014 so_base_ws_lo = lower_32_bits(CFG_BASE +
3016 so_base_ws_hi = upper_32_bits(CFG_BASE +
3061 lower_32_bits(CFG_BASE + irq_handler_offset));
3063 upper_32_bits(CFG_BASE + irq_handler_offset));
3111 so_base_hi = upper_32_bits(CFG_BASE +
3153 mtr_base_en_lo = lower_32_bits((CFG_BASE & U32_MAX) +
3155 mtr_base_en_hi = upper_32_bits(CFG_BASE +
3157 so_base_en_lo = lower_32_bits((CFG_BASE & U32_MAX) +
3159 so_base_en_hi = upper_32_bits(CFG_BASE +
3161 mtr_base_ws_lo = lower_32_bits((CFG_BASE & U32_MAX) +
3163 mtr_base_ws_hi = upper_32_bits(CFG_BASE +
3165 so_base_ws_lo = lower_32_bits((CFG_BASE & U32_MAX) +
3167 so_base_ws_hi = upper_32_bits(CFG_BASE +
3211 lower_32_bits(CFG_BASE + irq_handler_offset));
3213 upper_32_bits(CFG_BASE + irq_handler_offset));
3584 WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE, 0);
3587 WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE + 0xC, 0);
3588 WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE + 0x8, 0);
3591 WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE, 1);
3597 WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE, 0);
5560 cq_pkt->addr = cpu_to_le64(CFG_BASE + msi_addr);
5716 base_addr = CFG_BASE + mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0;
5724 base_addr = CFG_BASE + mmSYNC_MNGR_E_S_SYNC_MNGR_OBJS_SOB_OBJ_0;
5732 base_addr = CFG_BASE + mmSYNC_MNGR_W_N_SYNC_MNGR_OBJS_SOB_OBJ_0;
5740 base_addr = CFG_BASE + mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_STATUS_0;
5748 base_addr = CFG_BASE + mmSYNC_MNGR_E_S_SYNC_MNGR_OBJS_MON_STATUS_0;
5756 base_addr = CFG_BASE + mmSYNC_MNGR_W_N_SYNC_MNGR_OBJS_MON_STATUS_0;
5764 base_addr = CFG_BASE + mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_SOB_OBJ_0 +
5773 base_addr = CFG_BASE + mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_STATUS_0 +
5792 u64 sob_addr = CFG_BASE +
6725 if (params->block_address >= CFG_BASE)
6726 params->block_address -= CFG_BASE;
8225 lower_32_bits(CFG_BASE +
8683 *addr = CFG_BASE + offset;
8830 reg_value -= lower_32_bits(CFG_BASE);
9010 fence_cnt = base_offset + CFG_BASE +