Lines Matching defs:val
480 u32 size, u64 val);
482 u32 num_regs, u32 val);
1227 "Generate master wait CBs, sob %d (mask %#x), val:0x%x, mon %u, q %d\n",
1245 "Generate master wait CBs, sob %d (mask %#x), val:0x%x, mon %u, q %d\n",
1291 "Generate slave wait CB, sob %d, val:%x, mon %d, q %d\n",
1298 "generate signal CB, sob_id: %d, sob val: 1, q_idx: %d\n",
4558 static int gaudi_scrub_device_dram(struct hl_device *hdev, u64 val)
4577 lower_32_bits(val));
4579 upper_32_bits(val));
4624 u64 addr, size, val = hdev->memory_scrub_val;
4644 dev_dbg(hdev->dev, "Scrubbing SRAM: 0x%09llx - 0x%09llx val: 0x%llx\n",
4645 addr, addr + size, val);
4646 rc = gaudi_memset_device_memory(hdev, addr, size, val);
4653 rc = gaudi_scrub_device_dram(hdev, val);
5563 static void gaudi_update_eq_ci(struct hl_device *hdev, u32 val)
5565 WREG32(mmCPU_IF_EQ_RD_OFFS, val);
5569 u32 size, u64 val)
5592 lin_dma_pkt->src_addr = cpu_to_le64(val);
5648 u32 num_regs, u32 val)
5677 pkt->value = cpu_to_le32(val);
5879 u32 err_cause, val;
5896 val,
5897 ((val & DMA0_CORE_STS0_BUSY_MASK) == 0),
6039 static void gaudi_write_pte(struct hl_device *hdev, u64 addr, u64 val)
6046 writeq(val, hdev->pcie_bar[HBM_BAR_ID] +
6530 u32 val, x_y, axi_id;
6532 val = is_write ? RREG32(mmMMU_UP_RAZWI_WRITE_ID) :
6534 x_y = val & ((RAZWI_INITIATOR_Y_MASK << RAZWI_INITIATOR_Y_SHIFT) |
6536 axi_id = val & (RAZWI_INITIATOR_AXI_ID_MASK <<
6635 val,
6636 (val >> RAZWI_INITIATOR_Y_SHIFT) & RAZWI_INITIATOR_Y_MASK,
6637 (val >> RAZWI_INITIATOR_X_SHIFT) & RAZWI_INITIATOR_X_MASK,
6638 (val >> RAZWI_INITIATOR_AXI_ID_SHIFT) &
6668 u32 val;
6673 val = RREG32(mmMMU_UP_PAGE_ERROR_CAPTURE);
6674 if (val & MMU_UP_PAGE_ERROR_CAPTURE_ENTRY_VALID_MASK) {
6675 *addr = val & MMU_UP_PAGE_ERROR_CAPTURE_VA_49_32_MASK;
6685 val = RREG32(mmMMU_UP_ACCESS_ERROR_CAPTURE);
6686 if (val & MMU_UP_ACCESS_ERROR_CAPTURE_ENTRY_VALID_MASK) {
6687 *addr = val & MMU_UP_ACCESS_ERROR_CAPTURE_VA_49_32_MASK;
7339 u32 base, val, val2, wr_par, rd_par, ca_par, derr, serr, type, ch;
7382 val = RREG32_MASK(base + ch * 0x1000 + 0x06C, 0x0000FFFF);
7383 val = (val & 0xFF) | ((val >> 8) & 0xFF);
7384 if (val) {
7388 device, ch * 2, val & 0x1, (val >> 1) & 0x1,
7389 (val >> 2) & 0x1, (val >> 3) & 0x1,
7390 (val >> 4) & 0x1);
7402 val = RREG32_MASK(base + ch * 0x1000 + 0x07C, 0x0000FFFF);
7403 val = (val & 0xFF) | ((val >> 8) & 0xFF);
7404 if (val) {
7408 device, ch * 2 + 1, val & 0x1, (val >> 1) & 0x1,
7409 (val >> 2) & 0x1, (val >> 3) & 0x1,
7410 (val >> 4) & 0x1);
7431 val = RREG32(base + 0x8F30);
7433 if (val | val2) {
7437 device, val, val2);
7439 val = RREG32(base + 0x8F40);
7441 if (val | val2) {
7445 device, val, val2);
8949 "Mon id: %u%s, wait for group id: %u mask %s to reach val: %u and write %u to address 0x%llx. Pending: %s. Means sync objects [%s] are being monitored.",