Lines Matching defs:tpc_offset
2518 u32 tpc_offset;
2524 for (tpc_id = 0, tpc_offset = 0;
2526 tpc_id++, tpc_offset += TPC_CFG_OFFSET) {
2528 WREG32(mmTPC0_CFG_TPC_INTR_MASK + tpc_offset, 0x8FFE);
2530 WREG32_FIELD(TPC0_CFG_MSS_CONFIG, tpc_offset,
2992 static void gaudi_init_tpc_qman(struct hl_device *hdev, u32 tpc_offset,
3019 q_off = tpc_offset + qman_id * 4;
3021 tpc_id = tpc_offset /
3058 WREG32(mmTPC0_QM_GLBL_ERR_CFG + tpc_offset, tpc_qm_err_cfg);
3060 WREG32(mmTPC0_QM_GLBL_ERR_ADDR_LO + tpc_offset,
3062 WREG32(mmTPC0_QM_GLBL_ERR_ADDR_HI + tpc_offset,
3065 WREG32(mmTPC0_QM_GLBL_ERR_WDATA + tpc_offset,
3069 WREG32(mmTPC0_QM_ARB_ERR_MSG_EN + tpc_offset,
3073 WREG32(mmTPC0_QM_ARB_SLV_CHOISE_WDT + tpc_offset, GAUDI_ARB_WDT_TIMEOUT);
3075 WREG32(mmTPC0_QM_GLBL_CFG1 + tpc_offset, 0);
3076 WREG32(mmTPC0_QM_GLBL_PROT + tpc_offset,
3103 u32 so_base_hi, tpc_offset = 0;
3120 gaudi_init_tpc_qman(hdev, tpc_offset, i,
3125 gaudi_init_tpc_qman(hdev, tpc_offset, 4, 0);
3128 WREG32(mmTPC0_QM_GLBL_CFG0 + tpc_offset,
3136 tpc_offset += mmTPC1_QM_GLBL_CFG0 - mmTPC0_QM_GLBL_CFG0;
3323 u32 tpc_offset = 0;
3330 WREG32(mmTPC0_QM_GLBL_CFG0 + tpc_offset, 0);
3331 tpc_offset += mmTPC1_QM_GLBL_CFG0 - mmTPC0_QM_GLBL_CFG0;
7477 u32 tpc_offset = tpc_id * TPC_CFG_OFFSET, tpc_interrupts_cause, i;
7480 tpc_interrupts_cause = RREG32(mmTPC0_CFG_TPC_INTR_CAUSE + tpc_offset) &
7495 WREG32(mmTPC0_CFG_TPC_INTR_CAUSE + tpc_offset, 0);