Lines Matching defs:q_off
2551 u32 q_off, dma_qm_offset;
2573 q_off = dma_qm_offset + qman_id * 4;
2575 WREG32(mmDMA0_QM_PQ_BASE_LO_0 + q_off, lower_32_bits(qman_pq_addr));
2576 WREG32(mmDMA0_QM_PQ_BASE_HI_0 + q_off, upper_32_bits(qman_pq_addr));
2578 WREG32(mmDMA0_QM_PQ_SIZE_0 + q_off, ilog2(HL_QUEUE_LENGTH));
2579 WREG32(mmDMA0_QM_PQ_PI_0 + q_off, 0);
2580 WREG32(mmDMA0_QM_PQ_CI_0 + q_off, 0);
2582 WREG32(mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_0 + q_off, QMAN_LDMA_SIZE_OFFSET);
2583 WREG32(mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 + q_off,
2585 WREG32(mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 + q_off,
2588 WREG32(mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_0 + q_off, mtr_base_en_lo);
2589 WREG32(mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_0 + q_off, mtr_base_en_hi);
2590 WREG32(mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_0 + q_off, so_base_en_lo);
2591 WREG32(mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_0 + q_off, so_base_en_hi);
2592 WREG32(mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_0 + q_off, mtr_base_ws_lo);
2593 WREG32(mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_0 + q_off, mtr_base_ws_hi);
2594 WREG32(mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_0 + q_off, so_base_ws_lo);
2595 WREG32(mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_0 + q_off, so_base_ws_hi);
2597 WREG32(mmDMA0_QM_CP_BARRIER_CFG_0 + q_off, 0x100);
2732 u32 q_off, dma_qm_offset;
2753 q_off = dma_qm_offset + qman_id * 4;
2756 WREG32(mmDMA0_QM_PQ_BASE_LO_0 + q_off,
2758 WREG32(mmDMA0_QM_PQ_BASE_HI_0 + q_off,
2761 WREG32(mmDMA0_QM_PQ_SIZE_0 + q_off, ilog2(HBM_DMA_QMAN_LENGTH));
2762 WREG32(mmDMA0_QM_PQ_PI_0 + q_off, 0);
2763 WREG32(mmDMA0_QM_PQ_CI_0 + q_off, 0);
2765 WREG32(mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_0 + q_off,
2767 WREG32(mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 + q_off,
2769 WREG32(mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 + q_off,
2776 WREG32(mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_0 + q_off,
2778 WREG32(mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 + q_off,
2780 WREG32(mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 + q_off,
2811 WREG32(mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_0 + q_off, mtr_base_en_lo);
2812 WREG32(mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_0 + q_off, mtr_base_en_hi);
2813 WREG32(mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_0 + q_off, so_base_en_lo);
2814 WREG32(mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_0 + q_off, so_base_en_hi);
2818 WREG32(mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_0 + q_off,
2820 WREG32(mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_0 + q_off,
2822 WREG32(mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_0 + q_off,
2824 WREG32(mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_0 + q_off,
2874 u32 q_off, mme_id;
2886 q_off = mme_offset + qman_id * 4;
2889 WREG32(mmMME0_QM_PQ_BASE_LO_0 + q_off,
2891 WREG32(mmMME0_QM_PQ_BASE_HI_0 + q_off,
2894 WREG32(mmMME0_QM_PQ_SIZE_0 + q_off, ilog2(MME_QMAN_LENGTH));
2895 WREG32(mmMME0_QM_PQ_PI_0 + q_off, 0);
2896 WREG32(mmMME0_QM_PQ_CI_0 + q_off, 0);
2898 WREG32(mmMME0_QM_CP_LDMA_TSIZE_OFFSET_0 + q_off,
2900 WREG32(mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 + q_off,
2902 WREG32(mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 + q_off,
2909 WREG32(mmMME0_QM_CP_LDMA_TSIZE_OFFSET_0 + q_off,
2911 WREG32(mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 + q_off,
2913 WREG32(mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 + q_off,
2947 WREG32(mmMME0_QM_CP_MSG_BASE0_ADDR_LO_0 + q_off, mtr_base_lo);
2948 WREG32(mmMME0_QM_CP_MSG_BASE0_ADDR_HI_0 + q_off, mtr_base_hi);
2949 WREG32(mmMME0_QM_CP_MSG_BASE1_ADDR_LO_0 + q_off, so_base_lo);
2950 WREG32(mmMME0_QM_CP_MSG_BASE1_ADDR_HI_0 + q_off, so_base_hi);
3000 u32 q_off, tpc_id;
3019 q_off = tpc_offset + qman_id * 4;
3025 WREG32(mmTPC0_QM_PQ_BASE_LO_0 + q_off,
3027 WREG32(mmTPC0_QM_PQ_BASE_HI_0 + q_off,
3030 WREG32(mmTPC0_QM_PQ_SIZE_0 + q_off, ilog2(TPC_QMAN_LENGTH));
3031 WREG32(mmTPC0_QM_PQ_PI_0 + q_off, 0);
3032 WREG32(mmTPC0_QM_PQ_CI_0 + q_off, 0);
3034 WREG32(mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_0 + q_off,
3036 WREG32(mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 + q_off,
3038 WREG32(mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 + q_off,
3045 WREG32(mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_0 + q_off,
3047 WREG32(mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 + q_off,
3049 WREG32(mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 + q_off,
3080 WREG32(mmTPC0_QM_CP_MSG_BASE0_ADDR_LO_0 + q_off, mtr_base_en_lo);
3081 WREG32(mmTPC0_QM_CP_MSG_BASE0_ADDR_HI_0 + q_off, mtr_base_en_hi);
3082 WREG32(mmTPC0_QM_CP_MSG_BASE1_ADDR_LO_0 + q_off, so_base_en_lo);
3083 WREG32(mmTPC0_QM_CP_MSG_BASE1_ADDR_HI_0 + q_off, so_base_en_hi);
3087 WREG32(mmTPC0_QM_CP_MSG_BASE2_ADDR_LO_0 + q_off,
3089 WREG32(mmTPC0_QM_CP_MSG_BASE2_ADDR_HI_0 + q_off,
3091 WREG32(mmTPC0_QM_CP_MSG_BASE3_ADDR_LO_0 + q_off,
3093 WREG32(mmTPC0_QM_CP_MSG_BASE3_ADDR_HI_0 + q_off,
3151 u32 q_off;
3170 q_off = nic_offset + qman_id * 4;
3172 WREG32(mmNIC0_QM0_PQ_BASE_LO_0 + q_off, lower_32_bits(qman_base_addr));
3173 WREG32(mmNIC0_QM0_PQ_BASE_HI_0 + q_off, upper_32_bits(qman_base_addr));
3175 WREG32(mmNIC0_QM0_PQ_SIZE_0 + q_off, ilog2(NIC_QMAN_LENGTH));
3176 WREG32(mmNIC0_QM0_PQ_PI_0 + q_off, 0);
3177 WREG32(mmNIC0_QM0_PQ_CI_0 + q_off, 0);
3179 WREG32(mmNIC0_QM0_CP_LDMA_TSIZE_OFFSET_0 + q_off,
3181 WREG32(mmNIC0_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_0 + q_off,
3183 WREG32(mmNIC0_QM0_CP_LDMA_DST_BASE_LO_OFFSET_0 + q_off,
3186 WREG32(mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_0 + q_off, mtr_base_en_lo);
3187 WREG32(mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_0 + q_off, mtr_base_en_hi);
3188 WREG32(mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_0 + q_off, so_base_en_lo);
3189 WREG32(mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_0 + q_off, so_base_en_hi);
3192 WREG32(mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_0 + q_off, mtr_base_ws_lo);
3193 WREG32(mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_0 + q_off, mtr_base_ws_hi);
3194 WREG32(mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_0 + q_off, so_base_ws_lo);
3195 WREG32(mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_0 + q_off, so_base_ws_hi);
4188 u32 db_reg_offset, db_value, dma_qm_offset, q_off, irq_handler_offset;
4197 q_off = dma_qm_offset + (hw_queue_id & 0x3) * 4;
4198 db_reg_offset = mmDMA0_QM_PQ_PI_0 + q_off;
4204 q_off = dma_qm_offset + (hw_queue_id & 0x3) * 4;
4205 db_reg_offset = mmDMA0_QM_PQ_PI_0 + q_off;
4211 q_off = dma_qm_offset + ((hw_queue_id - 1) & 0x3) * 4;
4212 db_reg_offset = mmDMA0_QM_PQ_PI_0 + q_off;
4218 q_off = dma_qm_offset + ((hw_queue_id - 1) & 0x3) * 4;
4219 db_reg_offset = mmDMA0_QM_PQ_PI_0 + q_off;
4225 q_off = dma_qm_offset + ((hw_queue_id - 1) & 0x3) * 4;
4226 db_reg_offset = mmDMA0_QM_PQ_PI_0 + q_off;
4232 q_off = dma_qm_offset + ((hw_queue_id - 1) & 0x3) * 4;
4233 db_reg_offset = mmDMA0_QM_PQ_PI_0 + q_off;
4239 q_off = dma_qm_offset + ((hw_queue_id - 1) & 0x3) * 4;
4240 db_reg_offset = mmDMA0_QM_PQ_PI_0 + q_off;
4246 q_off = dma_qm_offset + ((hw_queue_id - 1) & 0x3) * 4;
4247 db_reg_offset = mmDMA0_QM_PQ_PI_0 + q_off;
4421 q_off = ((hw_queue_id - 1) & 0x3) * 4;
4422 db_reg_offset = mmNIC0_QM0_PQ_PI_0 + q_off;
4429 q_off = ((hw_queue_id - 1) & 0x3) * 4;
4430 db_reg_offset = mmNIC0_QM1_PQ_PI_0 + q_off;
4437 q_off = ((hw_queue_id - 1) & 0x3) * 4;
4438 db_reg_offset = mmNIC1_QM0_PQ_PI_0 + q_off;
4445 q_off = ((hw_queue_id - 1) & 0x3) * 4;
4446 db_reg_offset = mmNIC1_QM1_PQ_PI_0 + q_off;
4453 q_off = ((hw_queue_id - 1) & 0x3) * 4;
4454 db_reg_offset = mmNIC2_QM0_PQ_PI_0 + q_off;
4461 q_off = ((hw_queue_id - 1) & 0x3) * 4;
4462 db_reg_offset = mmNIC2_QM1_PQ_PI_0 + q_off;
4469 q_off = ((hw_queue_id - 1) & 0x3) * 4;
4470 db_reg_offset = mmNIC3_QM0_PQ_PI_0 + q_off;
4477 q_off = ((hw_queue_id - 1) & 0x3) * 4;
4478 db_reg_offset = mmNIC3_QM1_PQ_PI_0 + q_off;
4485 q_off = ((hw_queue_id - 1) & 0x3) * 4;
4486 db_reg_offset = mmNIC4_QM0_PQ_PI_0 + q_off;
4493 q_off = ((hw_queue_id - 1) & 0x3) * 4;
4494 db_reg_offset = mmNIC4_QM1_PQ_PI_0 + q_off;