Lines Matching refs:pwr
106 static u32 mid_pwr_get_state(struct mid_pwr *pwr, int reg)
108 return readl(pwr->regs + PM_SSS(reg));
111 static void mid_pwr_set_state(struct mid_pwr *pwr, int reg, u32 value)
113 writel(value, pwr->regs + PM_SSC(reg));
116 static void mid_pwr_set_wake(struct mid_pwr *pwr, int reg, u32 value)
118 writel(value, pwr->regs + PM_WKC(reg));
121 static void mid_pwr_interrupt_disable(struct mid_pwr *pwr)
123 writel(~PM_ICS_IE, pwr->regs + PM_ICS);
126 static bool mid_pwr_is_busy(struct mid_pwr *pwr)
128 return !!(readl(pwr->regs + PM_STS) & PM_STS_BUSY);
132 static int mid_pwr_wait(struct mid_pwr *pwr)
138 busy = mid_pwr_is_busy(pwr);
147 static int mid_pwr_wait_for_cmd(struct mid_pwr *pwr, u8 cmd)
149 writel(PM_CMD_CMD(cmd) | PM_CMD_CM_IMMEDIATE, pwr->regs + PM_CMD);
150 return mid_pwr_wait(pwr);
153 static int __update_power_state(struct mid_pwr *pwr, int reg, int bit, int new)
160 power = mid_pwr_get_state(pwr, reg);
166 mid_pwr_set_state(pwr, reg, (power & ~(3 << bit)) | (new << bit));
169 ret = mid_pwr_wait_for_cmd(pwr, CMD_SET_CFG);
174 power = mid_pwr_get_state(pwr, reg);
213 static int __set_power_state(struct mid_pwr *pwr, struct pci_dev *pdev,
219 state = __find_weakest_power_state(pwr->lss[id], pdev, state);
222 ret = __update_power_state(pwr, reg, bit, (__force int)state);
232 static int mid_pwr_set_power_state(struct mid_pwr *pwr, struct pci_dev *pdev,
251 mutex_lock(&pwr->lock);
252 ret = __set_power_state(pwr, pdev, state, id, reg, bit);
253 mutex_unlock(&pwr->lock);
259 struct mid_pwr *pwr = midpwr;
264 if (pwr && pwr->available)
265 ret = mid_pwr_set_power_state(pwr, pdev, state);
273 struct mid_pwr *pwr = midpwr;
277 if (!pwr || !pwr->available)
286 power = mid_pwr_get_state(pwr, reg);
292 struct mid_pwr *pwr = midpwr;
300 writel(cmd, pwr->regs + PM_CMD);
301 mid_pwr_wait(pwr);
331 struct mid_pwr *pwr = dev_id;
334 ics = readl(pwr->regs + PM_ICS);
338 writel(ics | PM_ICS_IP, pwr->regs + PM_ICS);
340 dev_warn(pwr->dev, "Unexpected IRQ: %#x\n", PM_ICS_INT_STATUS(ics));
345 int (*set_initial_state)(struct mid_pwr *pwr);
352 struct mid_pwr *pwr;
367 pwr = devm_kzalloc(dev, sizeof(*pwr), GFP_KERNEL);
368 if (!pwr)
371 pwr->dev = dev;
372 pwr->regs = pcim_iomap_table(pdev)[0];
373 pwr->irq = pdev->irq;
375 mutex_init(&pwr->lock);
378 mid_pwr_interrupt_disable(pwr);
381 ret = info->set_initial_state(pwr);
387 IRQF_NO_SUSPEND, pci_name(pdev), pwr);
391 pwr->available = true;
392 midpwr = pwr;
394 pci_set_drvdata(pdev, pwr);
398 static int mid_set_initial_state(struct mid_pwr *pwr, const u32 *states)
409 mid_pwr_set_wake(pwr, 0, 0xffffffff);
410 mid_pwr_set_wake(pwr, 1, 0xffffffff);
423 mid_pwr_set_state(pwr, 0, states[0]);
424 mid_pwr_set_state(pwr, 1, states[1]);
425 mid_pwr_set_state(pwr, 2, states[2]);
426 mid_pwr_set_state(pwr, 3, states[3]);
429 ret = mid_pwr_wait_for_cmd(pwr, CMD_SET_CFG);
435 pwr->lss[i][j].state = PCI_D3hot;
441 static int pnw_set_initial_state(struct mid_pwr *pwr)
450 return mid_set_initial_state(pwr, states);
453 static int tng_set_initial_state(struct mid_pwr *pwr)
461 return mid_set_initial_state(pwr, states);