Lines Matching defs:set
168 * tuning, i.e. allows privileged userspace to set an exact advancement time.
322 * When called, it means the previous get/set msr reached an invalid msr.
594 * FIXED_1 bits should always be set.
596 * Active high bits should be set if 1-setting in payload.
1089 * Do not allow the guest to set bits that we do not support
1090 * saving. However, xcr0 bit 0 is always set, even if the
1440 * the set of MSRs that KVM exposes to userspace through KVM_GET_MSRS,
1549 * KVM would refuse to load in the first place if the core set of MSRs
1574 * that are effectively CPUID leafs. VMX MSRs are also included in the set of
1664 * TSX_CTRL: some buggy userspaces leave it set on tsx=on hosts,
2375 /* we verify if the enable bit is set... */
2478 /* set tsc_scaling_ratio to a safe value */
2625 * according to the spec this should set L1's TSC (as opposed to
3130 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
3382 * HWCR[McStatusWrEn] is set.
4269 * are set to zero, indicating minimum divisors for
4365 * @return number of msrs set successfully.
4384 * @return number of msrs set successfully.
5061 * - none of the bits for Machine Check Exceptions are set
5062 * - both the VAL (valid) and UC (uncorrectable) bits are set
5177 * KVM_CAP_EXCEPTION_PAYLOAD, is not set, userspace may or may not
5476 * EINVAL is returned when the host attempts to set the flag for a guest that
6749 * in use, we use master_kernel_ns + kvmclock_offset to set
8741 * This is correct even for TF set by the guest, because "the
9264 * correct TSC value must be set before the request. However,
9266 * starts running in hardware virtualization between the set
9484 * with an exception. PAT[0] is set to WB on RESET and also by the
9755 enum kvm_apicv_inhibit reason, bool set)
9757 if (set)
9762 trace_kvm_apicv_inhibit_changed(reason, set, *inhibits);
10140 * VM-Exits cannot be injected (flag should _never_ be set).
10154 * Fault-class exceptions, except #DBs, set RF=1 in the RFLAGS
10161 * fault-like. They do _not_ set RF, a la code breakpoints.
10353 * pending. At the same time, KVM_REQ_EVENT may not be set as APICv was
10390 enum kvm_apicv_inhibit reason, bool set)
10401 set_or_clear_apicv_inhibit(&new, reason, set);
10431 enum kvm_apicv_inhibit reason, bool set)
10437 __kvm_set_or_clear_apicv_inhibit(kvm, reason, set);
10713 * 1) We should set ->mode before checking ->requests. Please see
10716 * 2) For APICv, we should set ->mode before checking PID.ON. This
10799 * can (a) read the correct value of the debug registers, (b) set
11174 * If userspace set a pending exception and L2 is active, convert it to
11482 * When EFER.LME and CR0.PG are set, the processor is in
11484 * CR4.PAE and EFER.LMA must be set.
11645 bool set = false;
11656 set = true;
11660 __kvm_set_or_clear_apicv_inhibit(kvm, APICV_INHIBIT_REASON_BLOCKIRQ, set);
11883 * the set of vCPUs). Opportunistically mark APICv active as
12026 * Several of the "set" flows, e.g. ->set_cr0(), read other registers
12128 * CR0.CD/NW are set on RESET, preserved on INIT. Note, some versions
12129 * of Intel's SDM list CD/NW as being set on INIT, but they contradict
12239 * why we set last_host_tsc to the local tsc observed here.
12242 * as that is the only way backwards_tsc is set above. Also note
12744 * Initially-all-set does not require write protecting any page,
12795 * writable bit was set. I.e. KVM is almost guaranteed to need
13277 uint32_t guest_irq, bool set)
13279 return static_call(kvm_x86_pi_update_irte)(kvm, host_irq, guest_irq, set);