Lines Matching defs:entries
1233 * the invalidation, but the guest's TLB entries need to be flushed as
1234 * the CPU may have cached entries in its TLB for the target PCID.
3001 /* no guest entries from this point */
3016 /* guest entries allowed */
4368 struct kvm_msr_entry *entries,
4375 if (do_msr(vcpu, entries[i].index, &entries[i].data))
4392 struct kvm_msr_entry *entries;
4405 entries = memdup_user(user_msrs->entries, size);
4406 if (IS_ERR(entries)) {
4407 r = PTR_ERR(entries);
4411 r = __msr_io(vcpu, &msrs, entries, do_msr);
4413 if (writeback && copy_to_user(user_msrs->entries, entries, size))
4416 kfree(entries);
4438 r = kvm_get_hv_cpuid(vcpu, &cpuid, cpuid_arg->entries);
4729 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
5723 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
5734 cpuid_arg->entries);
5745 cpuid_arg->entries);
8480 * u32 for select entries will leave some chunks uninitialized.
8492 * There's currently space for 13 entries, but 5 are used for the exit
9206 /* no guest entries from this point */
10553 * Note, the order matters here, as flushing "all" TLB entries
10554 * also flushes the "current" TLB entries, i.e. servicing the
12157 * Intel's SDM states that all TLB entries are flushed on INIT. AMD's
12779 * Because CPUs may have stale TLB entries at this point, a
12792 * CPU doesn't contain stale, writable TLB entries for a
13425 * Currently, KVM doesn't mark global entries in the shadow
13428 * keeping track of global entries in shadow page tables.