Lines Matching defs:event
28 * event is enumerated via CPUID using the index of the event.
41 * Pseudo-architectural event used to implement IA32_FIXED_CTR2, a.k.a.
42 * TSC reference cycles. The architectural reference cycles event may
247 if (lbr_desc->event) {
248 perf_event_release_kernel(lbr_desc->event);
249 lbr_desc->event = NULL;
258 struct perf_event *event;
263 * cpu pinned event reclaims LBR, the event->oncpu will be set to -1;
267 * schedule the event without a real HW counter but a fake one;
273 * event, which helps KVM to save/restore guest LBR records
288 if (unlikely(lbr_desc->event)) {
293 event = perf_event_create_kernel_counter(&attr, -1,
295 if (IS_ERR(event)) {
297 __func__, PTR_ERR(event));
298 return PTR_ERR(event);
300 lbr_desc->event = event;
309 * the LBR msrs records when the guest LBR event is scheduled in.
320 if (!lbr_desc->event && intel_pmu_create_guest_lbr_event(vcpu) < 0)
330 if (lbr_desc->event->state == PERF_EVENT_STATE_ACTIVE) {
478 u32 event = fixed_pmc_events[index];
480 pmc->eventsel = (intel_arch_events[event].unit_mask << 8) |
481 intel_arch_events[event].eventsel;
629 lbr_desc->event = NULL;
720 if (!lbr_desc->event) {
729 if (lbr_desc->event->state < PERF_EVENT_STATE_ACTIVE) {
762 * A negative index indicates the event isn't mapped to a