Lines Matching defs:false
89 { .index = MSR_IA32_SYSENTER_EIP, .always = false },
90 { .index = MSR_IA32_SYSENTER_ESP, .always = false },
99 { .index = MSR_IA32_SPEC_CTRL, .always = false },
100 { .index = MSR_IA32_PRED_CMD, .always = false },
101 { .index = MSR_IA32_FLUSH_CMD, .always = false },
102 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
103 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
104 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
105 { .index = MSR_IA32_LASTINTTOIP, .always = false },
106 { .index = MSR_EFER, .always = false },
107 { .index = MSR_IA32_CR_PAT, .always = false },
109 { .index = MSR_TSC_AUX, .always = false },
110 { .index = X2APIC_MSR(APIC_ID), .always = false },
111 { .index = X2APIC_MSR(APIC_LVR), .always = false },
112 { .index = X2APIC_MSR(APIC_TASKPRI), .always = false },
113 { .index = X2APIC_MSR(APIC_ARBPRI), .always = false },
114 { .index = X2APIC_MSR(APIC_PROCPRI), .always = false },
115 { .index = X2APIC_MSR(APIC_EOI), .always = false },
116 { .index = X2APIC_MSR(APIC_RRR), .always = false },
117 { .index = X2APIC_MSR(APIC_LDR), .always = false },
118 { .index = X2APIC_MSR(APIC_DFR), .always = false },
119 { .index = X2APIC_MSR(APIC_SPIV), .always = false },
120 { .index = X2APIC_MSR(APIC_ISR), .always = false },
121 { .index = X2APIC_MSR(APIC_TMR), .always = false },
122 { .index = X2APIC_MSR(APIC_IRR), .always = false },
123 { .index = X2APIC_MSR(APIC_ESR), .always = false },
124 { .index = X2APIC_MSR(APIC_ICR), .always = false },
125 { .index = X2APIC_MSR(APIC_ICR2), .always = false },
134 { .index = X2APIC_MSR(APIC_LVTTHMR), .always = false },
135 { .index = X2APIC_MSR(APIC_LVTPC), .always = false },
136 { .index = X2APIC_MSR(APIC_LVT0), .always = false },
137 { .index = X2APIC_MSR(APIC_LVT1), .always = false },
138 { .index = X2APIC_MSR(APIC_LVTERR), .always = false },
139 { .index = X2APIC_MSR(APIC_TMICT), .always = false },
140 { .index = X2APIC_MSR(APIC_TMCCT), .always = false },
141 { .index = X2APIC_MSR(APIC_TDCR), .always = false },
142 { .index = MSR_INVALID, .always = false },
539 return false;
544 return false;
549 return false;
555 return false;
1073 svm->nmi_singlestep = false;
1404 svm->nmi_masked = false;
1405 svm->awaiting_iret_completion = false;
1482 svm->guest_state_loaded = false;
1508 * The vmcb page can be recycled, causing a false negative in
1564 to_svm(vcpu)->guest_state_loaded = false;
2143 return false;
2147 return false;
2153 return false;
2311 return vmload_vmsave_interception(vcpu, false);
2477 svm_set_gif(to_svm(vcpu), false);
2518 bool has_error_code = false;
2537 vcpu->arch.nmi_injected = false;
2624 bool ret = false;
2628 return false;
2820 msr_info.host_initiated = false;
3224 * set in_kernel to false as well.
3594 return false;
3604 return false;
3607 return false;
3755 return false;
3795 return false;
4028 svm->nmi_l1_to_l2 = false;
4029 svm->soft_int_injected = false;
4037 svm->awaiting_iret_completion = false;
4038 svm->nmi_masked = false;
4042 vcpu->arch.nmi_injected = false;
4077 kvm_queue_interrupt(vcpu, vector, false);
4302 return false;
4305 return false;
4306 /* SEV-ES guests do not support SMM, so report false */
4308 return false;
4704 ret = enter_svm_guest_mode(vcpu, smram64->svm_guest_vmcb_gpa, vmcb12, false);
4752 return false;
4787 return false;
4873 return false;
5190 tsc_scaling = false;
5223 npt_enabled = false;
5226 npt_enabled = false;
5268 vls = false;
5275 svm_gp_erratum_intercept = false;
5279 vgif = false;
5296 lbrv = false;