Lines Matching refs:vmcb
577 if (svm->vcpu.guest_debug || (svm->vmcb->save.dr7 & ~DR7_FIXED_1))
586 memcpy(save, &svm->vmcb->save, sizeof(svm->vmcb->save));
1751 dst_svm->vmcb->control.ghcb_gpa = src_svm->vmcb->control.ghcb_gpa;
1752 dst_svm->vmcb->control.vmsa_pa = src_svm->vmcb->control.vmsa_pa;
1756 src_svm->vmcb->control.ghcb_gpa = INVALID_PAGE;
1757 src_svm->vmcb->control.vmsa_pa = INVALID_PAGE;
2385 pr_err("GHCB (GPA=%016llx):\n", svm->vmcb->control.ghcb_gpa);
2418 struct vmcb_control_area *control = &svm->vmcb->control;
2446 svm->vmcb->save.cpl = kvm_ghcb_get_cpl_if_valid(svm, ghcb);
2472 struct vmcb_control_area *control = &svm->vmcb->control;
2641 if (sd->sev_vmcbs[asid] == svm->vmcb &&
2645 sd->sev_vmcbs[asid] = svm->vmcb;
2646 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
2647 vmcb_mark_dirty(svm->vmcb, VMCB_ASID);
2653 struct vmcb_control_area *control = &svm->vmcb->control;
2738 svm->vmcb->control.ghcb_gpa &= ~(mask << pos);
2739 svm->vmcb->control.ghcb_gpa |= (value & mask) << pos;
2744 return (svm->vmcb->control.ghcb_gpa >> pos) & mask;
2749 svm->vmcb->control.ghcb_gpa = value;
2754 struct vmcb_control_area *control = &svm->vmcb->control;
2841 struct vmcb_control_area *control = &svm->vmcb->control;
2950 if (svm->vmcb->control.exit_info_2 > INT_MAX)
2953 count = svm->vmcb->control.exit_info_2;
2993 struct vmcb *vmcb = svm->vmcb01.ptr;
2996 svm->vmcb->control.nested_ctl |= SVM_NESTED_CTL_SEV_ES_ENABLE;
2997 svm->vmcb->control.virt_ext |= LBR_CTL_ENABLE_MASK;
3007 svm->vmcb->control.vmsa_pa = __pa(svm->sev_es.vmsa);
3025 vmcb->control.intercepts[INTERCEPT_DR] = 0;
3027 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR7_READ);
3028 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR7_WRITE);
3057 svm->vmcb->control.nested_ctl |= SVM_NESTED_CTL_SEV_ENABLE;