Lines Matching refs:hpet_base
36 struct hpet_base {
62 static struct hpet_base hpet_base;
196 hd.hd_nirqs = hpet_base.nr_channels;
206 for (i = 0; i < hpet_base.nr_channels; i++) {
207 struct hpet_channel *hc = hpet_base.channels + i;
231 for (i = 0; i < hpet_base.nr_channels; i++) {
232 struct hpet_channel *hc = hpet_base.channels + i;
672 for (i = 0; i < hpet_base.nr_channels; i++) {
673 struct hpet_channel *hc = hpet_base.channels + i;
708 hpet_base.nr_clockevents = 0;
720 for (i = 0; i < hpet_base.nr_channels; i++) {
721 struct hpet_channel *hc = hpet_base.channels + i;
740 if (++hpet_base.nr_clockevents == num_possible_cpus())
745 hpet_base.nr_channels, hpet_base.nr_clockevents);
1055 hpet_base.channels = hc;
1056 hpet_base.nr_channels = channels;
1060 hpet_base.boot_cfg = cfg;
1099 hpet_legacy_clockevent_register(&hpet_base.channels[0]);
1100 hpet_base.channels[0].mode = HPET_MODE_LEGACY;
1102 hpet_base.channels[1].mode = HPET_MODE_LEGACY;
1108 kfree(hpet_base.channels);
1109 hpet_base.channels = NULL;
1110 hpet_base.nr_channels = 0;
1150 if (!hpet_base.nr_clockevents)
1178 cfg = hpet_base.boot_cfg;
1183 for (i = 0; i < hpet_base.nr_channels; i++)
1184 hpet_writel(hpet_base.channels[i].boot_cfg, HPET_Tn_CFG(i));
1187 if (hpet_base.boot_cfg & HPET_CFG_ENABLE)
1188 hpet_writel(hpet_base.boot_cfg, HPET_CFG);
1284 struct clock_event_device *evt = &hpet_base.channels[0].evt;
1382 struct clock_event_device *evt = &hpet_base.channels[0].evt;