Lines Matching refs:val
166 u64 val;
171 rdmsrl(MSR_IA32_MCx_CTL2(bank), val);
174 val |= MCI_CTL2_CMCI_EN;
176 val &= ~MCI_CTL2_CMCI_EN;
178 wrmsrl(MSR_IA32_MCx_CTL2(bank), val);
283 u64 val;
293 rdmsrl(MSR_IA32_MCx_CTL2(i), val);
296 if (val & MCI_CTL2_CMCI_EN) {
303 val &= ~MCI_CTL2_CMCI_THRESHOLD_MASK;
304 val |= CMCI_THRESHOLD;
305 } else if (!(val & MCI_CTL2_CMCI_THRESHOLD_MASK)) {
312 val |= CMCI_THRESHOLD;
315 val |= MCI_CTL2_CMCI_EN;
316 wrmsrl(MSR_IA32_MCx_CTL2(i), val);
317 rdmsrl(MSR_IA32_MCx_CTL2(i), val);
320 if (val & MCI_CTL2_CMCI_EN) {
330 (val & MCI_CTL2_CMCI_THRESHOLD_MASK))
365 u64 val;
369 rdmsrl(MSR_IA32_MCx_CTL2(bank), val);
370 val &= ~MCI_CTL2_CMCI_EN;
371 wrmsrl(MSR_IA32_MCx_CTL2(bank), val);
467 u64 val;
472 rdmsrl(MSR_IA32_MCG_EXT_CTL, val);
474 if (!(val & MCG_EXT_CTL_LMCE_EN))
475 wrmsrl(MSR_IA32_MCG_EXT_CTL, val | MCG_EXT_CTL_LMCE_EN);
480 u64 val;
485 rdmsrl(MSR_IA32_MCG_EXT_CTL, val);
486 val &= ~MCG_EXT_CTL_LMCE_EN;
487 wrmsrl(MSR_IA32_MCG_EXT_CTL, val);