Lines Matching refs:nr
48 #define CONST_MASK_ADDR(nr, addr) WBYTE_ADDR((void *)(addr) + ((nr)>>3))
49 #define CONST_MASK(nr) (1 << ((nr) & 7))
52 arch_set_bit(long nr, volatile unsigned long *addr)
54 if (__builtin_constant_p(nr)) {
56 : CONST_MASK_ADDR(nr, addr)
57 : "iq" (CONST_MASK(nr))
61 : : RLONG_ADDR(addr), "Ir" (nr) : "memory");
66 arch___set_bit(unsigned long nr, volatile unsigned long *addr)
68 asm volatile(__ASM_SIZE(bts) " %1,%0" : : ADDR, "Ir" (nr) : "memory");
72 arch_clear_bit(long nr, volatile unsigned long *addr)
74 if (__builtin_constant_p(nr)) {
76 : CONST_MASK_ADDR(nr, addr)
77 : "iq" (~CONST_MASK(nr)));
80 : : RLONG_ADDR(addr), "Ir" (nr) : "memory");
85 arch_clear_bit_unlock(long nr, volatile unsigned long *addr)
88 arch_clear_bit(nr, addr);
92 arch___clear_bit(unsigned long nr, volatile unsigned long *addr)
94 asm volatile(__ASM_SIZE(btr) " %1,%0" : : ADDR, "Ir" (nr) : "memory");
98 arch_clear_bit_unlock_is_negative_byte(long nr, volatile unsigned long *addr)
104 : "ir" ((char) ~(1 << nr)) : "memory");
111 arch___clear_bit_unlock(long nr, volatile unsigned long *addr)
113 arch___clear_bit(nr, addr);
117 arch___change_bit(unsigned long nr, volatile unsigned long *addr)
119 asm volatile(__ASM_SIZE(btc) " %1,%0" : : ADDR, "Ir" (nr) : "memory");
123 arch_change_bit(long nr, volatile unsigned long *addr)
125 if (__builtin_constant_p(nr)) {
127 : CONST_MASK_ADDR(nr, addr)
128 : "iq" (CONST_MASK(nr)));
131 : : RLONG_ADDR(addr), "Ir" (nr) : "memory");
136 arch_test_and_set_bit(long nr, volatile unsigned long *addr)
138 return GEN_BINARY_RMWcc(LOCK_PREFIX __ASM_SIZE(bts), *addr, c, "Ir", nr);
142 arch_test_and_set_bit_lock(long nr, volatile unsigned long *addr)
144 return arch_test_and_set_bit(nr, addr);
148 arch___test_and_set_bit(unsigned long nr, volatile unsigned long *addr)
155 : ADDR, "Ir" (nr) : "memory");
160 arch_test_and_clear_bit(long nr, volatile unsigned long *addr)
162 return GEN_BINARY_RMWcc(LOCK_PREFIX __ASM_SIZE(btr), *addr, c, "Ir", nr);
174 arch___test_and_clear_bit(unsigned long nr, volatile unsigned long *addr)
181 : ADDR, "Ir" (nr) : "memory");
186 arch___test_and_change_bit(unsigned long nr, volatile unsigned long *addr)
193 : ADDR, "Ir" (nr) : "memory");
199 arch_test_and_change_bit(long nr, volatile unsigned long *addr)
201 return GEN_BINARY_RMWcc(LOCK_PREFIX __ASM_SIZE(btc), *addr, c, "Ir", nr);
204 static __always_inline bool constant_test_bit(long nr, const volatile unsigned long *addr)
206 return ((1UL << (nr & (BITS_PER_LONG-1))) &
207 (addr[nr >> _BITOPS_LONG_SHIFT])) != 0;
210 static __always_inline bool constant_test_bit_acquire(long nr, const volatile unsigned long *addr)
217 : "m" (((unsigned char *)addr)[nr >> 3]),
218 "i" (1 << (nr & 7))
224 static __always_inline bool variable_test_bit(long nr, volatile const unsigned long *addr)
231 : "m" (*(unsigned long *)addr), "Ir" (nr) : "memory");
237 arch_test_bit(unsigned long nr, const volatile unsigned long *addr)
239 return __builtin_constant_p(nr) ? constant_test_bit(nr, addr) :
240 variable_test_bit(nr, addr);
244 arch_test_bit_acquire(unsigned long nr, const volatile unsigned long *addr)
246 return __builtin_constant_p(nr) ? constant_test_bit_acquire(nr, addr) :
247 variable_test_bit(nr, addr);