Lines Matching refs:config
96 u64 config = event->attr.config;
98 return ((config & ARCH_PERFMON_EVENTSEL_EVENT) == 0) &&
99 ((config & INTEL_ARCH_EVENT_MASK) >= INTEL_TD_METRIC_RETIRING) &&
100 ((config & INTEL_ARCH_EVENT_MASK) <= INTEL_TD_METRIC_MAX);
105 return (event->attr.config & INTEL_ARCH_EVENT_MASK) == INTEL_TD_SLOTS;
168 u64 config; /* extra MSR config */
804 ssize_t (*events_sysfs_show)(char *page, u64 config);
1150 wrmsrl(hwc->extra_reg.reg, hwc->extra_reg.config);
1159 wrmsrl(hwc->config_base, (hwc->config | enable_mask) & ~disable_mask);
1175 wrmsrl(hwc->config_base, hwc->config & ~disable_mask);
1285 ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event);
1286 ssize_t intel_event_sysfs_show(char *page, u64 config);
1428 hw_event = hwc->config & INTEL_ARCH_EVENT_MASK;
1486 void intel_pmu_enable_bts(u64 config);