Lines Matching defs:event
123 PMU_EVENT_ATTR_STRING(tsc, attr_tsc, "event=0x00" );
124 PMU_EVENT_ATTR_STRING(aperf, attr_aperf, "event=0x01" );
125 PMU_EVENT_ATTR_STRING(mperf, attr_mperf, "event=0x02" );
126 PMU_EVENT_ATTR_STRING(pperf, attr_pperf, "event=0x03" );
127 PMU_EVENT_ATTR_STRING(smi, attr_smi, "event=0x04" );
128 PMU_EVENT_ATTR_STRING(ptsc, attr_ptsc, "event=0x05" );
129 PMU_EVENT_ATTR_STRING(irperf, attr_irperf, "event=0x06" );
130 PMU_EVENT_ATTR_STRING(cpu_thermal_margin, attr_therm, "event=0x07" );
176 PMU_FORMAT_ATTR(event, "config:0-63");
203 static int msr_event_init(struct perf_event *event)
205 u64 cfg = event->attr.config;
207 if (event->attr.type != event->pmu->type)
211 if (event->attr.sample_period) /* no sampling */
222 event->hw.idx = -1;
223 event->hw.event_base = msr[cfg].msr;
224 event->hw.config = cfg;
229 static inline u64 msr_read_counter(struct perf_event *event)
233 if (event->hw.event_base)
234 rdmsrl(event->hw.event_base, now);
241 static void msr_event_update(struct perf_event *event)
246 /* Careful, an NMI might modify the previous event value: */
247 prev = local64_read(&event->hw.prev_count);
249 now = msr_read_counter(event);
250 } while (!local64_try_cmpxchg(&event->hw.prev_count, &prev, now));
253 if (unlikely(event->hw.event_base == MSR_SMI_COUNT)) {
255 local64_add(delta, &event->count);
256 } else if (unlikely(event->hw.event_base == MSR_IA32_THERM_STATUS)) {
259 local64_set(&event->count, now);
261 local64_add(delta, &event->count);
265 static void msr_event_start(struct perf_event *event, int flags)
267 u64 now = msr_read_counter(event);
269 local64_set(&event->hw.prev_count, now);
272 static void msr_event_stop(struct perf_event *event, int flags)
274 msr_event_update(event);
277 static void msr_event_del(struct perf_event *event, int flags)
279 msr_event_stop(event, PERF_EF_UPDATE);
282 static int msr_event_add(struct perf_event *event, int flags)
285 msr_event_start(event, flags);