Lines Matching refs:x86_pmu
129 if (pmi && x86_pmu.version >= 4)
137 lbr_select = cpuc->lbr_sel->config & x86_pmu.lbr_sel_mask;
167 for (i = 0; i < x86_pmu.lbr_nr; i++)
168 wrmsrl(x86_pmu.lbr_from + i, 0);
175 for (i = 0; i < x86_pmu.lbr_nr; i++) {
176 wrmsrl(x86_pmu.lbr_from + i, 0);
177 wrmsrl(x86_pmu.lbr_to + i, 0);
178 if (x86_pmu.lbr_has_info)
179 wrmsrl(x86_pmu.lbr_info + i, 0);
186 wrmsrl(MSR_ARCH_LBR_DEPTH, x86_pmu.lbr_nr);
193 if (!x86_pmu.lbr_nr)
196 x86_pmu.lbr_reset();
211 rdmsrl(x86_pmu.lbr_tos, tos);
284 wrmsrl(x86_pmu.lbr_from + idx, val);
289 wrmsrl(x86_pmu.lbr_to + idx, val);
294 wrmsrl(x86_pmu.lbr_info + idx, val);
304 rdmsrl(x86_pmu.lbr_from + idx, val);
316 rdmsrl(x86_pmu.lbr_to + idx, val);
328 rdmsrl(x86_pmu.lbr_info + idx, val);
363 bool need_info = x86_pmu.lbr_has_info;
368 mask = x86_pmu.lbr_nr - 1;
374 for (; i < x86_pmu.lbr_nr; i++) {
382 wrmsrl(x86_pmu.lbr_tos, tos);
395 if (!entries[x86_pmu.lbr_nr - 1].from)
398 for (i = 0; i < x86_pmu.lbr_nr; i++) {
419 return x86_pmu.lbr_deep_c_reset && !rdlbr_from(0, NULL);
446 x86_pmu.lbr_restore(ctx);
455 bool need_info = x86_pmu.lbr_has_info;
460 mask = x86_pmu.lbr_nr - 1;
462 for (i = 0; i < x86_pmu.lbr_nr; i++) {
480 for (i = 0; i < x86_pmu.lbr_nr; i++) {
486 if (i < x86_pmu.lbr_nr)
487 entries[x86_pmu.lbr_nr - 1].from = 0;
510 x86_pmu.lbr_save(ctx);
582 if (!x86_pmu.lbr_nr)
612 if (x86_pmu.intel_cap.pebs_baseline && event->attr.precise_ip > 0)
663 if (!x86_pmu.lbr_nr)
673 if (x86_pmu.intel_cap.pebs_baseline && event->attr.precise_ip > 0)
711 unsigned long mask = x86_pmu.lbr_nr - 1;
716 for (i = 0; i < x86_pmu.lbr_nr; i++) {
726 rdmsrl(x86_pmu.lbr_from + lbr_idx, msr_lastbranch.lbr);
746 unsigned long mask = x86_pmu.lbr_nr - 1;
751 int num = x86_pmu.lbr_nr;
774 if (x86_pmu.lbr_has_info) {
782 if (x86_pmu.lbr_has_tsx) {
790 if (x86_pmu.lbr_from_flags) {
795 if (x86_pmu.lbr_has_tsx) {
802 if (x86_pmu.lbr_to_cycles) {
816 if (abort && x86_pmu.lbr_double_abort && out > 0)
877 for (i = 0; i < x86_pmu.lbr_nr; i++) {
938 x86_pmu.lbr_read(cpuc);
1027 v = x86_pmu.lbr_sel_map[i];
1058 reg->config = mask ^ (x86_pmu.lbr_sel_mask & ~LBR_CALL_STACK);
1062 x86_pmu.lbr_has_info)
1075 if (!x86_pmu.lbr_nr)
1088 if (x86_pmu.lbr_sel_map)
1277 x86_pmu.lbr_nr = 4;
1278 x86_pmu.lbr_tos = MSR_LBR_TOS;
1279 x86_pmu.lbr_from = MSR_LBR_CORE_FROM;
1280 x86_pmu.lbr_to = MSR_LBR_CORE_TO;
1291 x86_pmu.lbr_nr = 16;
1292 x86_pmu.lbr_tos = MSR_LBR_TOS;
1293 x86_pmu.lbr_from = MSR_LBR_NHM_FROM;
1294 x86_pmu.lbr_to = MSR_LBR_NHM_TO;
1296 x86_pmu.lbr_sel_mask = LBR_SEL_MASK;
1297 x86_pmu.lbr_sel_map = nhm_lbr_sel_map;
1311 x86_pmu.lbr_nr = 16;
1312 x86_pmu.lbr_tos = MSR_LBR_TOS;
1313 x86_pmu.lbr_from = MSR_LBR_NHM_FROM;
1314 x86_pmu.lbr_to = MSR_LBR_NHM_TO;
1316 x86_pmu.lbr_sel_mask = LBR_SEL_MASK;
1317 x86_pmu.lbr_sel_map = snb_lbr_sel_map;
1338 x86_pmu.lbr_nr = 16;
1339 x86_pmu.lbr_tos = MSR_LBR_TOS;
1340 x86_pmu.lbr_from = MSR_LBR_NHM_FROM;
1341 x86_pmu.lbr_to = MSR_LBR_NHM_TO;
1343 x86_pmu.lbr_sel_mask = LBR_SEL_MASK;
1344 x86_pmu.lbr_sel_map = hsw_lbr_sel_map;
1354 x86_pmu.lbr_nr = 32;
1355 x86_pmu.lbr_tos = MSR_LBR_TOS;
1356 x86_pmu.lbr_from = MSR_LBR_NHM_FROM;
1357 x86_pmu.lbr_to = MSR_LBR_NHM_TO;
1358 x86_pmu.lbr_info = MSR_LBR_INFO_0;
1360 x86_pmu.lbr_sel_mask = LBR_SEL_MASK;
1361 x86_pmu.lbr_sel_map = hsw_lbr_sel_map;
1387 x86_pmu.lbr_nr = 8;
1388 x86_pmu.lbr_tos = MSR_LBR_TOS;
1389 x86_pmu.lbr_from = MSR_LBR_CORE_FROM;
1390 x86_pmu.lbr_to = MSR_LBR_CORE_TO;
1401 x86_pmu.lbr_nr = 8;
1402 x86_pmu.lbr_tos = MSR_LBR_TOS;
1403 x86_pmu.lbr_from = MSR_LBR_CORE_FROM;
1404 x86_pmu.lbr_to = MSR_LBR_CORE_TO;
1406 x86_pmu.lbr_sel_mask = LBR_SEL_MASK;
1407 x86_pmu.lbr_sel_map = nhm_lbr_sel_map;
1419 x86_pmu.lbr_nr = 8;
1420 x86_pmu.lbr_tos = MSR_LBR_TOS;
1421 x86_pmu.lbr_from = MSR_LBR_NHM_FROM;
1422 x86_pmu.lbr_to = MSR_LBR_NHM_TO;
1424 x86_pmu.lbr_sel_mask = LBR_SEL_MASK;
1425 x86_pmu.lbr_sel_map = snb_lbr_sel_map;
1428 if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_LIP)
1429 x86_pmu.intel_cap.lbr_format = LBR_FORMAT_EIP_FLAGS;
1434 switch (x86_pmu.intel_cap.lbr_format) {
1436 x86_pmu.lbr_has_tsx = 1;
1437 x86_pmu.lbr_from_flags = 1;
1443 x86_pmu.lbr_from_flags = 1;
1447 x86_pmu.lbr_has_tsx = 1;
1450 x86_pmu.lbr_has_info = 1;
1454 x86_pmu.lbr_from_flags = 1;
1455 x86_pmu.lbr_to_cycles = 1;
1459 if (x86_pmu.lbr_has_info) {
1476 x86_pmu.lbr_nr * sizeof(struct lbr_entry);
1519 x86_pmu.lbr_depth_mask = eax.split.lbr_depth_mask;
1520 x86_pmu.lbr_deep_c_reset = eax.split.lbr_deep_c_reset;
1521 x86_pmu.lbr_lip = eax.split.lbr_lip;
1522 x86_pmu.lbr_cpl = ebx.split.lbr_cpl;
1523 x86_pmu.lbr_filter = ebx.split.lbr_filter;
1524 x86_pmu.lbr_call_stack = ebx.split.lbr_call_stack;
1525 x86_pmu.lbr_mispred = ecx.split.lbr_mispred;
1526 x86_pmu.lbr_timed_lbr = ecx.split.lbr_timed_lbr;
1527 x86_pmu.lbr_br_type = ecx.split.lbr_br_type;
1528 x86_pmu.lbr_nr = lbr_nr;
1530 if (x86_pmu.lbr_mispred)
1532 if (x86_pmu.lbr_timed_lbr)
1534 if (x86_pmu.lbr_br_type)
1553 x86_pmu.lbr_from = MSR_ARCH_LBR_FROM_0;
1554 x86_pmu.lbr_to = MSR_ARCH_LBR_TO_0;
1555 x86_pmu.lbr_info = MSR_ARCH_LBR_INFO_0;
1558 if (!x86_pmu.lbr_cpl ||
1559 !x86_pmu.lbr_filter ||
1560 !x86_pmu.lbr_call_stack)
1563 if (!x86_pmu.lbr_cpl) {
1566 } else if (!x86_pmu.lbr_filter) {
1576 x86_pmu.lbr_ctl_mask = ARCH_LBR_CTL_MASK;
1577 x86_pmu.lbr_ctl_map = arch_lbr_ctl_map;
1579 if (!x86_pmu.lbr_cpl && !x86_pmu.lbr_filter)
1580 x86_pmu.lbr_ctl_map = NULL;
1582 x86_pmu.lbr_reset = intel_pmu_arch_lbr_reset;
1584 x86_pmu.lbr_save = intel_pmu_arch_lbr_xsaves;
1585 x86_pmu.lbr_restore = intel_pmu_arch_lbr_xrstors;
1586 x86_pmu.lbr_read = intel_pmu_arch_lbr_read_xsave;
1589 x86_pmu.lbr_save = intel_pmu_arch_lbr_save;
1590 x86_pmu.lbr_restore = intel_pmu_arch_lbr_restore;
1591 x86_pmu.lbr_read = intel_pmu_arch_lbr_read;
1609 lbr->nr = x86_pmu.lbr_nr;
1610 lbr->from = x86_pmu.lbr_from;
1611 lbr->to = x86_pmu.lbr_to;
1612 lbr->info = x86_pmu.lbr_info;