Lines Matching defs:dse
177 union intel_x86_pebs_dse dse;
180 dse.val = status;
189 if (dse.st_stlb_miss)
199 if (dse.st_l1d_hit)
207 if (dse.st_locked)
215 union perf_mem_data_src dse;
217 dse.val = PERF_MEM_NA;
220 dse.mem_op = PERF_MEM_OP_STORE;
222 dse.mem_op = PERF_MEM_OP_LOAD;
234 dse.mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_HIT;
236 dse.mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_MISS;
238 return dse.val;
260 u8 dse, bool tlb, bool lock, bool blk)
266 dse &= PERF_PEBS_DATA_SOURCE_MASK;
267 val = hybrid_var(event->pmu, pebs_data_source)[dse];
281 union intel_x86_pebs_dse dse;
283 dse.val = status;
285 return __adl_latency_data_small(event, status, dse.ld_dse,
286 dse.ld_locked, dse.ld_stlb_miss,
287 dse.ld_data_blk);
293 union intel_x86_pebs_dse dse;
295 dse.val = status;
297 return __adl_latency_data_small(event, status, dse.mtl_dse,
298 dse.mtl_stlb_miss, dse.mtl_locked,
299 dse.mtl_fwd_blk);
304 union intel_x86_pebs_dse dse;
307 dse.val = status;
312 val = hybrid_var(event->pmu, pebs_data_source)[dse.ld_dse];
322 pebs_set_tlb_lock(&val, dse.ld_stlb_miss, dse.ld_locked);
335 if (dse.ld_data_blk)
342 if (dse.ld_addr_blk)
345 if (!dse.ld_data_blk && !dse.ld_addr_blk)
353 union intel_x86_pebs_dse dse;
357 dse.val = status;
362 val = hybrid_var(event->pmu, pebs_data_source)[dse.st_lat_dse];
364 pebs_set_tlb_lock(&val, dse.st_lat_stlb_miss, dse.st_lat_locked);
392 u64 status, dla, dse, lat;
404 u64 status, dla, dse, lat;
433 u64 status, dla, dse, lat;
1647 data->data_src.val = get_data_src(event, pebs->dse);