Lines Matching defs:msr
85 unsigned int msr;
325 hwc->config_base = perf_ibs->msr;
669 .msr = MSR_AMD64_IBSFETCHCTL,
693 .msr = MSR_AMD64_IBSOPCTL,
924 #define ibs_op_msr_idx(msr) (msr - MSR_AMD64_IBSOPCTL)
1029 unsigned int msr;
1050 msr = hwc->config_base;
1052 rdmsrl(msr, *buf);
1070 rdmsrl(msr + offset, *buf++);
1385 * the offset in the IBS_CTL per-node msr. The per-core APIC setup of