Lines Matching defs:chan
154 static int __init phy_wait_for_ack(struct pci_channel *chan)
159 if (pci_read_reg(chan, SH4A_PCIEPHYADRR) & (1 << BITS_ACK))
168 static int __init pci_wait_for_irq(struct pci_channel *chan, unsigned int mask)
173 if ((pci_read_reg(chan, SH4A_PCIEINTR) & mask) == mask)
182 static void __init phy_write_reg(struct pci_channel *chan, unsigned int addr,
191 pci_write_reg(chan, data, SH4A_PCIEPHYDOUTR);
192 pci_write_reg(chan, phyaddr, SH4A_PCIEPHYADRR);
194 phy_wait_for_ack(chan);
197 pci_write_reg(chan, 0, SH4A_PCIEPHYDOUTR);
198 pci_write_reg(chan, 0, SH4A_PCIEPHYADRR);
200 phy_wait_for_ack(chan);
205 struct pci_channel *chan = port->hose;
240 clk->enable_reg = (void __iomem *)(chan->reg_base + SH4A_PCIEPHYCTLR);
260 struct pci_channel *chan = port->hose;
266 phy_write_reg(chan, 0x60, 0xf, 0x004b008b);
267 phy_write_reg(chan, 0x61, 0xf, 0x00007b41);
268 phy_write_reg(chan, 0x64, 0xf, 0x00ff4f00);
269 phy_write_reg(chan, 0x65, 0xf, 0x09070907);
270 phy_write_reg(chan, 0x66, 0xf, 0x00000010);
271 phy_write_reg(chan, 0x74, 0xf, 0x0007001c);
272 phy_write_reg(chan, 0x79, 0xf, 0x01fc000d);
273 phy_write_reg(chan, 0xb0, 0xf, 0x00000610);
276 phy_write_reg(chan, 0x67, 0x1, 0x00000400);
282 if (pci_read_reg(chan, SH4A_PCIEPHYSR))
293 struct pci_channel *chan = port->hose;
295 pci_write_reg(chan, 1, SH4A_PCIESRSTR);
296 pci_write_reg(chan, 0, SH4A_PCIETCTLR);
297 pci_write_reg(chan, 0, SH4A_PCIESRSTR);
298 pci_write_reg(chan, 0, SH4A_PCIETXVC0SR);
303 struct pci_channel *chan = port->hose;
316 pci_write_reg(chan, PCI_CLASS_BRIDGE_PCI_NORMAL << 8, SH4A_PCIEIDSETR1);
319 data = pci_read_reg(chan, SH4A_PCIEEXPCAP0);
328 pci_write_reg(chan, data, SH4A_PCIEEXPCAP0);
331 pci_write_reg(chan, PCI_EXP_LNKCAP_DLLLARC, SH4A_PCIEEXPCAP3);
334 data = pci_read_reg(chan, SH4A_PCIEEXPCAP4);
337 pci_write_reg(chan, data, SH4A_PCIEEXPCAP4);
340 data = pci_read_reg(chan, SH4A_PCIEEXPCAP5);
343 pci_write_reg(chan, data, SH4A_PCIEEXPCAP5);
346 data = pci_read_reg(chan, SH4A_PCIETLCTLR);
349 pci_write_reg(chan, data, SH4A_PCIETLCTLR);
355 data = pci_read_reg(chan, SH4A_PCIEMACCTLR);
358 pci_write_reg(chan, data, SH4A_PCIEMACCTLR);
377 pci_write_reg(chan, memstart + SZ_512M, SH4A_PCIELAR1);
378 pci_write_reg(chan, ((memsize - SZ_512M) - SZ_256) | 1,
385 pci_write_reg(chan, 0, SH4A_PCIELAR1);
386 pci_write_reg(chan, 0, SH4A_PCIELAMR1);
393 pci_write_reg(chan, memstart, SH4A_PCIELAR0);
394 pci_write_reg(chan, (memsize - SZ_256) | 1, SH4A_PCIELAMR0);
397 data = pci_read_reg(chan, SH4A_PCIETCTLR);
399 pci_write_reg(chan, data, SH4A_PCIETCTLR);
405 data = pci_read_reg(chan, SH4A_PCIEDLINTENR);
407 pci_write_reg(chan, data, SH4A_PCIEDLINTENR);
410 data = pci_read_reg(chan, SH4A_PCIEMACCTLR);
412 pci_write_reg(chan, data, SH4A_PCIEMACCTLR);
419 ret = pci_wait_for_irq(chan, MASK_INT_TX_CTRL);
421 data = pci_read_reg(chan, SH4A_PCIEPCICONF1);
425 pci_write_reg(chan, data, SH4A_PCIEPCICONF1);
427 pci_write_reg(chan, 0x80888000, SH4A_PCIETXVC0DCTLR);
428 pci_write_reg(chan, 0x00222000, SH4A_PCIERXVC0DCTLR);
433 data = pci_read_reg(chan, SH4A_PCIEMACSR);
440 for (i = win = 0; i < chan->nr_resources; i++) {
441 struct resource *res = chan->resources + i;
455 pci_write_reg(chan, 0x00000000, SH4A_PCIEPTCTLR(win));
463 pci_write_reg(chan, mask << 18, SH4A_PCIEPAMR(win));
465 pci_write_reg(chan, upper_32_bits(res->start),
467 pci_write_reg(chan, lower_32_bits(res->start),
474 pci_write_reg(chan, mask, SH4A_PCIEPTCTLR(win));