Lines Matching defs:imm
166 /* Emit variable-length instructions for 32-bit and 64-bit imm */
483 static void emit_atomic(u8 rd, u8 rs, s16 off, s32 imm, bool is64,
499 switch (imm) {
1078 s32 imm = insn->imm;
1086 if (imm == 1) {
1194 /* dst = BSWAP##imm(dst) */
1196 switch (imm) {
1219 if (imm == 16)
1231 if (imm == 32)
1260 /* dst = imm */
1263 emit_imm(rd, imm, ctx);
1268 /* dst = dst OP imm */
1271 if (is_12b_int(imm)) {
1272 emit_addi(rd, rd, imm, ctx);
1274 emit_imm(RV_REG_T1, imm, ctx);
1282 if (is_12b_int(-imm)) {
1283 emit_addi(rd, rd, -imm, ctx);
1285 emit_imm(RV_REG_T1, imm, ctx);
1293 if (is_12b_int(imm)) {
1294 emit_andi(rd, rd, imm, ctx);
1296 emit_imm(RV_REG_T1, imm, ctx);
1304 if (is_12b_int(imm)) {
1305 emit(rv_ori(rd, rd, imm), ctx);
1307 emit_imm(RV_REG_T1, imm, ctx);
1315 if (is_12b_int(imm)) {
1316 emit(rv_xori(rd, rd, imm), ctx);
1318 emit_imm(RV_REG_T1, imm, ctx);
1326 emit_imm(RV_REG_T1, imm, ctx);
1334 emit_imm(RV_REG_T1, imm, ctx);
1346 emit_imm(RV_REG_T1, imm, ctx);
1358 emit_slli(rd, rd, imm, ctx);
1366 emit_srli(rd, rd, imm, ctx);
1368 emit(rv_srliw(rd, rd, imm), ctx);
1376 emit_srai(rd, rd, imm, ctx);
1378 emit(rv_sraiw(rd, rd, imm), ctx);
1390 rvoff = rv_offset(i, imm, ctx);
1443 /* IF (dst COND imm) JUMP off */
1466 if (imm) {
1467 emit_imm(RV_REG_T1, imm, ctx);
1470 /* If imm is 0, simply use zero register. */
1490 if (is_12b_int(imm)) {
1491 emit_andi(RV_REG_T1, rd, imm, ctx);
1493 emit_imm(RV_REG_T1, imm, ctx);
1500 if (!is64 && imm < 0)
1550 imm64 = (u64)insn1.imm << 32 | (u32)imm;
1675 /* ST: *(size *)(dst + off) = imm */
1677 emit_imm(RV_REG_T1, imm, ctx);
1689 emit_imm(RV_REG_T1, imm, ctx);
1700 emit_imm(RV_REG_T1, imm, ctx);
1711 emit_imm(RV_REG_T1, imm, ctx);
1765 emit_atomic(rd, rs, off, imm,