Lines Matching defs:reg_num

124 	unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |
132 	switch (reg_num) {
173 	unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |
184 	switch (reg_num) {
278 	unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |
285 	if (reg_num >= sizeof(struct kvm_riscv_core) / sizeof(unsigned long))
288 	if (reg_num == KVM_REG_RISCV_CORE_REG(regs.pc))
290 	else if (KVM_REG_RISCV_CORE_REG(regs.pc) < reg_num &&
291 		 reg_num <= KVM_REG_RISCV_CORE_REG(regs.t6))
292 		reg_val = ((unsigned long *)cntx)[reg_num];
293 	else if (reg_num == KVM_REG_RISCV_CORE_REG(mode))
311 	unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |
318 	if (reg_num >= sizeof(struct kvm_riscv_core) / sizeof(unsigned long))
324 	if (reg_num == KVM_REG_RISCV_CORE_REG(regs.pc))
326 	else if (KVM_REG_RISCV_CORE_REG(regs.pc) < reg_num &&
327 		 reg_num <= KVM_REG_RISCV_CORE_REG(regs.t6))
328 		((unsigned long *)cntx)[reg_num] = reg_val;
329 	else if (reg_num == KVM_REG_RISCV_CORE_REG(mode)) {
341 					  unsigned long reg_num,
346 	if (reg_num >= sizeof(struct kvm_riscv_csr) / sizeof(unsigned long))
349 	if (reg_num == KVM_REG_RISCV_CSR_REG(sip)) {
354 		*out_val = ((unsigned long *)csr)[reg_num];
360 					  unsigned long reg_num,
365 	if (reg_num >= sizeof(struct kvm_riscv_csr) / sizeof(unsigned long))
368 	if (reg_num == KVM_REG_RISCV_CSR_REG(sip)) {
373 	((unsigned long *)csr)[reg_num] = reg_val;
375 	if (reg_num == KVM_REG_RISCV_CSR_REG(sip))
387 	unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |
395 	reg_subtype = reg_num & KVM_REG_RISCV_SUBTYPE_MASK;
396 	reg_num &= ~KVM_REG_RISCV_SUBTYPE_MASK;
399 		rc = kvm_riscv_vcpu_general_get_csr(vcpu, reg_num, &reg_val);
402 		rc = kvm_riscv_vcpu_aia_get_csr(vcpu, reg_num, &reg_val);
423 	unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |
434 	reg_subtype = reg_num & KVM_REG_RISCV_SUBTYPE_MASK;
435 	reg_num &= ~KVM_REG_RISCV_SUBTYPE_MASK;
438 		rc = kvm_riscv_vcpu_general_set_csr(vcpu, reg_num, reg_val);
441 		rc = kvm_riscv_vcpu_aia_set_csr(vcpu, reg_num, reg_val);
454 					 unsigned long reg_num,
459 	if (reg_num >= KVM_RISCV_ISA_EXT_MAX ||
460 	    reg_num >= ARRAY_SIZE(kvm_isa_ext_arr))
463 	host_isa_ext = kvm_isa_ext_arr[reg_num];
475 					 unsigned long reg_num,
480 	if (reg_num >= KVM_RISCV_ISA_EXT_MAX ||
481 	    reg_num >= ARRAY_SIZE(kvm_isa_ext_arr))
484 	host_isa_ext = kvm_isa_ext_arr[reg_num];
497 		    kvm_riscv_vcpu_isa_enable_allowed(reg_num))
500 			 kvm_riscv_vcpu_isa_disable_allowed(reg_num))
513 					unsigned long reg_num,
518 	if (reg_num > KVM_REG_RISCV_ISA_MULTI_REG_LAST)
522 		ext_id = i + reg_num * BITS_PER_LONG;
536 					unsigned long reg_num,
541 	if (reg_num > KVM_REG_RISCV_ISA_MULTI_REG_LAST)
545 		ext_id = i + reg_num * BITS_PER_LONG;
561 	unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |
569 	reg_subtype = reg_num & KVM_REG_RISCV_SUBTYPE_MASK;
570 	reg_num &= ~KVM_REG_RISCV_SUBTYPE_MASK;
575 		rc = riscv_vcpu_get_isa_ext_single(vcpu, reg_num, &reg_val);
579 		rc = riscv_vcpu_get_isa_ext_multi(vcpu, reg_num, &reg_val);
600 	unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |
608 	reg_subtype = reg_num & KVM_REG_RISCV_SUBTYPE_MASK;
609 	reg_num &= ~KVM_REG_RISCV_SUBTYPE_MASK;
616 		return riscv_vcpu_set_isa_ext_single(vcpu, reg_num, reg_val);
618 		return riscv_vcpu_set_isa_ext_multi(vcpu, reg_num, reg_val, true);
620 		return riscv_vcpu_set_isa_ext_multi(vcpu, reg_num, reg_val, false);