Lines Matching refs:RB
540 /* The RB field in an X, XO, M, or MDS form instruction. */
541 #define RB RAOPT + 1
545 /* The RB field in an X form instruction when it must be the same as
548 #define RBS RB + 1
551 /* The RB field in an lswx instruction, which has special value
556 /* The RB field of the dccci and iccci instructions, which are optional. */
1785 /* The RB field in an X form instruction when it must be the same as
1810 /* The RB field in an lswx instruction, which has special value
2632 /* An XX1_MASK with the RB field fixed. */
2684 /* An X_MASK with the RB field fixed. */
2693 /* An X_MASK with the RA and RB fields fixed. */
2696 /* An XBF_MASK with the RA and RB fields fixed. */
2708 /* An X_MASK with the RT and RB fields fixed. */
2714 /* An X_MASK with the RT, RA and RB fields fixed. */
2792 /* An XL_MASK with the RT, RA and RB fields fixed, but S bit clear. */
2833 /* An XO_MASK with the RB field fixed. */
3102 {"psq_lx", XW (4, 6,0), XW_MASK, PPCPS, 0, {FRT,RA,RB,PSWM,PSQM}},
3104 {"psq_stx", XW (4, 7,0), XW_MASK, PPCPS, 0, {FRS,RA,RB,PSWM,PSQM}},
3106 {"mulhhwu", XRC(4, 8,0), X_MASK, MULHW, 0, {RT, RA, RB}},
3107 {"mulhhwu.", XRC(4, 8,1), X_MASK, MULHW, 0, {RT, RA, RB}},
3113 {"machhwu", XO (4, 12,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3115 {"machhwu.", XO (4, 12,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3147 {"maddhd", VXA(4, 48), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}},
3149 {"maddhdu", VXA(4, 49), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}},
3152 {"maddld", VXA(4, 51), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}},
3177 {"psq_lux", XW (4, 38,0), XW_MASK, PPCPS, 0, {FRT,RA,RB,PSWM,PSQM}},
3179 {"psq_stux", XW (4, 39,0), XW_MASK, PPCPS, 0, {FRS,RA,RB,PSWM,PSQM}},
3182 {"mulhhw", XRC(4, 40,0), X_MASK, MULHW, 0, {RT, RA, RB}},
3184 {"mulhhw.", XRC(4, 40,1), X_MASK, MULHW, 0, {RT, RA, RB}},
3185 {"machhw", XO (4, 44,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3186 {"machhw.", XO (4, 44,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3187 {"nmachhw", XO (4, 46,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3188 {"nmachhw.", XO (4, 46,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3202 {"machhwsu", XO (4, 76,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3203 {"machhwsu.", XO (4, 76,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3212 {"machhws", XO (4, 108,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3213 {"machhws.", XO (4, 108,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3214 {"nmachhws", XO (4, 110,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3215 {"nmachhws.", XO (4, 110,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3225 {"mulchwu", XRC(4, 136,0), X_MASK, MULHW, 0, {RT, RA, RB}},
3227 {"mulchwu.", XRC(4, 136,1), X_MASK, MULHW, 0, {RT, RA, RB}},
3228 {"macchwu", XO (4, 140,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3229 {"macchwu.", XO (4, 140,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3238 {"mulchw", XRC(4, 168,0), X_MASK, MULHW, 0, {RT, RA, RB}},
3239 {"mulchw.", XRC(4, 168,1), X_MASK, MULHW, 0, {RT, RA, RB}},
3240 {"macchw", XO (4, 172,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3241 {"macchw.", XO (4, 172,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3242 {"nmacchw", XO (4, 174,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3243 {"nmacchw.", XO (4, 174,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3253 {"macchwsu", XO (4, 204,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3254 {"macchwsu.", XO (4, 204,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3261 {"macchws", XO (4, 236,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3262 {"macchws.", XO (4, 236,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3263 {"nmacchws", XO (4, 238,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3264 {"nmacchws.", XO (4, 238,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3265 {"evaddw", VX (4, 512), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3268 {"evaddiw", VX (4, 514), VX_MASK, PPCSPE, 0, {RS, RB, UIMM}},
3270 {"evsubfw", VX (4, 516), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3271 {"evsubw", VX (4, 516), VX_MASK, PPCSPE, 0, {RS, RB, RA}},
3273 {"evsubifw", VX (4, 518), VX_MASK, PPCSPE, 0, {RS, UIMM, RB}},
3274 {"evsubiw", VX (4, 518), VX_MASK, PPCSPE, 0, {RS, RB, UIMM}},
3288 {"brinc", VX (4, 527), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3291 {"evand", VX (4, 529), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3292 {"evandc", VX (4, 530), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3293 {"evxor", VX (4, 534), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3295 {"evor", VX (4, 535), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3296 {"evnor", VX (4, 536), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3299 {"eveqv", VX (4, 537), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3300 {"evorc", VX (4, 539), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3301 {"evnand", VX (4, 542), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3302 {"evsrwu", VX (4, 544), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3303 {"evsrws", VX (4, 545), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3306 {"evslw", VX (4, 548), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3308 {"evrlw", VX (4, 552), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3312 {"evmergehi", VX (4, 556), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3313 {"evmergelo", VX (4, 557), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3314 {"evmergehilo", VX (4, 558), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3315 {"evmergelohi", VX (4, 559), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3316 {"evcmpgtu", VX (4, 560), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3317 {"evcmpgts", VX (4, 561), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3318 {"evcmpltu", VX (4, 562), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3319 {"evcmplts", VX (4, 563), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3320 {"evcmpeq", VX (4, 564), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3333 {"evsel", EVSEL(4,79), EVSEL_MASK, PPCSPE, 0, {RS, RA, RB, CRFS}},
3335 {"evfsadd", VX (4, 640), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3337 {"evfssub", VX (4, 641), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3345 {"evfsmul", VX (4, 648), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3346 {"evfsdiv", VX (4, 649), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3348 {"evfscmpgt", VX (4, 652), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3351 {"evfscmplt", VX (4, 653), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3352 {"evfscmpeq", VX (4, 654), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3354 {"evfscfui", VX (4, 656), VX_MASK, PPCSPE, 0, {RS, RB}},
3355 {"evfscfsi", VX (4, 657), VX_MASK, PPCSPE, 0, {RS, RB}},
3356 {"evfscfuf", VX (4, 658), VX_MASK, PPCSPE, 0, {RS, RB}},
3357 {"evfscfsf", VX (4, 659), VX_MASK, PPCSPE, 0, {RS, RB}},
3358 {"evfsctui", VX (4, 660), VX_MASK, PPCSPE, 0, {RS, RB}},
3359 {"evfsctsi", VX (4, 661), VX_MASK, PPCSPE, 0, {RS, RB}},
3360 {"evfsctuf", VX (4, 662), VX_MASK, PPCSPE, 0, {RS, RB}},
3361 {"evfsctsf", VX (4, 663), VX_MASK, PPCSPE, 0, {RS, RB}},
3362 {"evfsctuiz", VX (4, 664), VX_MASK, PPCSPE, 0, {RS, RB}},
3364 {"evfsctsiz", VX (4, 666), VX_MASK, PPCSPE, 0, {RS, RB}},
3365 {"evfststgt", VX (4, 668), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3366 {"evfststlt", VX (4, 669), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3367 {"evfststeq", VX (4, 670), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3369 {"efsadd", VX (4, 704), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3370 {"efssub", VX (4, 705), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3378 {"efsmul", VX (4, 712), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3379 {"efsdiv", VX (4, 713), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3381 {"efscmpgt", VX (4, 716), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3383 {"efscmplt", VX (4, 717), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3384 {"efscmpeq", VX (4, 718), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3386 {"efscfd", VX (4, 719), VX_MASK, PPCEFS, 0, {RS, RB}},
3387 {"efscfui", VX (4, 720), VX_MASK, PPCEFS, 0, {RS, RB}},
3388 {"efscfsi", VX (4, 721), VX_MASK, PPCEFS, 0, {RS, RB}},
3389 {"efscfuf", VX (4, 722), VX_MASK, PPCEFS, 0, {RS, RB}},
3390 {"efscfsf", VX (4, 723), VX_MASK, PPCEFS, 0, {RS, RB}},
3391 {"efsctui", VX (4, 724), VX_MASK, PPCEFS, 0, {RS, RB}},
3392 {"efsctsi", VX (4, 725), VX_MASK, PPCEFS, 0, {RS, RB}},
3393 {"efsctuf", VX (4, 726), VX_MASK, PPCEFS, 0, {RS, RB}},
3394 {"efsctsf", VX (4, 727), VX_MASK, PPCEFS, 0, {RS, RB}},
3395 {"efsctuiz", VX (4, 728), VX_MASK, PPCEFS, 0, {RS, RB}},
3397 {"efsctsiz", VX (4, 730), VX_MASK, PPCEFS, 0, {RS, RB}},
3398 {"efststgt", VX (4, 732), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3399 {"efststlt", VX (4, 733), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3400 {"efststeq", VX (4, 734), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3401 {"efdadd", VX (4, 736), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3402 {"efdsub", VX (4, 737), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3403 {"efdcfuid", VX (4, 738), VX_MASK, PPCEFS, 0, {RS, RB}},
3404 {"efdcfsid", VX (4, 739), VX_MASK, PPCEFS, 0, {RS, RB}},
3408 {"efdmul", VX (4, 744), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3409 {"efddiv", VX (4, 745), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3410 {"efdctuidz", VX (4, 746), VX_MASK, PPCEFS, 0, {RS, RB}},
3411 {"efdctsidz", VX (4, 747), VX_MASK, PPCEFS, 0, {RS, RB}},
3412 {"efdcmpgt", VX (4, 748), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3413 {"efdcmplt", VX (4, 749), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3414 {"efdcmpeq", VX (4, 750), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3415 {"efdcfs", VX (4, 751), VX_MASK, PPCEFS, 0, {RS, RB}},
3416 {"efdcfui", VX (4, 752), VX_MASK, PPCEFS, 0, {RS, RB}},
3417 {"efdcfsi", VX (4, 753), VX_MASK, PPCEFS, 0, {RS, RB}},
3418 {"efdcfuf", VX (4, 754), VX_MASK, PPCEFS, 0, {RS, RB}},
3419 {"efdcfsf", VX (4, 755), VX_MASK, PPCEFS, 0, {RS, RB}},
3420 {"efdctui", VX (4, 756), VX_MASK, PPCEFS, 0, {RS, RB}},
3421 {"efdctsi", VX (4, 757), VX_MASK, PPCEFS, 0, {RS, RB}},
3422 {"efdctuf", VX (4, 758), VX_MASK, PPCEFS, 0, {RS, RB}},
3423 {"efdctsf", VX (4, 759), VX_MASK, PPCEFS, 0, {RS, RB}},
3424 {"efdctuiz", VX (4, 760), VX_MASK, PPCEFS, 0, {RS, RB}},
3426 {"efdctsiz", VX (4, 762), VX_MASK, PPCEFS, 0, {RS, RB}},
3427 {"efdtstgt", VX (4, 764), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3428 {"efdtstlt", VX (4, 765), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3429 {"efdtsteq", VX (4, 766), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3430 {"evlddx", VX (4, 768), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3433 {"evldwx", VX (4, 770), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3436 {"evldhx", VX (4, 772), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3440 {"evlhhesplatx",VX (4, 776), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3445 {"evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3449 {"evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3452 {"mullhwu", XRC(4, 392,0), X_MASK, MULHW, 0, {RT, RA, RB}},
3453 {"evlwhex", VX (4, 784), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3454 {"mullhwu.", XRC(4, 392,1), X_MASK, MULHW, 0, {RT, RA, RB}},
3456 {"evlwhoux", VX (4, 788), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3458 {"evlwhosx", VX (4, 790), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3460 {"maclhwu", XO (4, 396,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}},
3461 {"evlwwsplatx", VX (4, 792), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3462 {"maclhwu.", XO (4, 396,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}},
3464 {"evlwhsplatx", VX (4, 796), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3466 {"evstddx", VX (4, 800), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3468 {"evstdwx", VX (4, 802), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3470 {"evstdhx", VX (4, 804), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3472 {"evstwhex", VX (4, 816), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3474 {"evstwhox", VX (4, 820), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3476 {"evstwwex", VX (4, 824), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3478 {"evstwwox", VX (4, 828), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3491 {"mullhw", XRC(4, 424,0), X_MASK, MULHW, 0, {RT, RA, RB}},
3492 {"mullhw.", XRC(4, 424,1), X_MASK, MULHW, 0, {RT, RA, RB}},
3493 {"maclhw", XO (4, 428,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}},
3494 {"maclhw.", XO (4, 428,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}},
3495 {"nmaclhw", XO (4, 430,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}},
3496 {"nmaclhw.", XO (4, 430,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}},
3506 {"maclhwsu", XO (4, 460,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3507 {"maclhwsu.", XO (4, 460,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3516 {"maclhws", XO (4, 492,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3517 {"maclhws.", XO (4, 492,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3518 {"nmaclhws", XO (4, 494,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3519 {"nmaclhws.", XO (4, 494,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3524 {"evmhessf", VX (4,1027), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3530 {"evmhossf", VX (4,1031), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3532 {"evmheumi", VX (4,1032), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3533 {"evmhesmi", VX (4,1033), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3535 {"evmhesmf", VX (4,1035), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3536 {"evmhoumi", VX (4,1036), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3538 {"evmhosmi", VX (4,1037), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3539 {"evmhosmf", VX (4,1039), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3540 {"machhwuo", XO (4, 12,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3541 {"machhwuo.", XO (4, 12,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3544 {"evmhessfa", VX (4,1059), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3545 {"evmhossfa", VX (4,1063), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3546 {"evmheumia", VX (4,1064), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3547 {"evmhesmia", VX (4,1065), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3548 {"evmhesmfa", VX (4,1067), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3549 {"evmhoumia", VX (4,1068), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3550 {"evmhosmia", VX (4,1069), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3551 {"evmhosmfa", VX (4,1071), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3561 {"evmwhssf", VX (4,1095), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3563 {"evmwlumi", VX (4,1096), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3565 {"evmwhumi", VX (4,1100), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3567 {"evmwhsmi", VX (4,1101), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3569 {"evmwhsmf", VX (4,1103), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3570 {"evmwssf", VX (4,1107), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3571 {"machhwo", XO (4, 44,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3572 {"evmwumi", VX (4,1112), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3573 {"machhwo.", XO (4, 44,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3574 {"evmwsmi", VX (4,1113), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3575 {"evmwsmf", VX (4,1115), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3576 {"nmachhwo", XO (4, 46,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3577 {"nmachhwo.", XO (4, 46,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3580 {"evmwhssfa", VX (4,1127), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3581 {"evmwlumia", VX (4,1128), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3582 {"evmwhumia", VX (4,1132), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3583 {"evmwhsmia", VX (4,1133), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3584 {"evmwhsmfa", VX (4,1135), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3585 {"evmwssfa", VX (4,1139), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3586 {"evmwumia", VX (4,1144), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3587 {"evmwsmia", VX (4,1145), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3588 {"evmwsmfa", VX (4,1147), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3600 {"machhwsuo", XO (4, 76,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3601 {"machhwsuo.", XO (4, 76,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3612 {"evdivws", VX (4,1222), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3617 {"evdivwu", VX (4,1223), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3624 {"machhwso", XO (4, 108,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3625 {"machhwso.", XO (4, 108,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3626 {"nmachhwso", XO (4, 110,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3627 {"nmachhwso.", XO (4, 110,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3631 {"evmheusiaaw", VX (4,1280), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3633 {"evmhessiaaw", VX (4,1281), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3635 {"evmhessfaaw", VX (4,1283), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3636 {"evmhousiaaw", VX (4,1284), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3639 {"evmhossiaaw", VX (4,1285), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3643 {"evmhossfaaw", VX (4,1287), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3644 {"evmheumiaaw", VX (4,1288), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3647 {"evmhesmiaaw", VX (4,1289), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3648 {"evmhesmfaaw", VX (4,1291), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3650 {"evmhoumiaaw", VX (4,1292), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3651 {"evmhosmiaaw", VX (4,1293), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3652 {"evmhosmfaaw", VX (4,1295), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3653 {"macchwuo", XO (4, 140,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3654 {"macchwuo.", XO (4, 140,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3655 {"evmhegumiaa", VX (4,1320), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3656 {"evmhegsmiaa", VX (4,1321), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3657 {"evmhegsmfaa", VX (4,1323), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3658 {"evmhogumiaa", VX (4,1324), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3659 {"evmhogsmiaa", VX (4,1325), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3660 {"evmhogsmfaa", VX (4,1327), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3662 {"evmwlusiaaw", VX (4,1344), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3664 {"evmwlssiaaw", VX (4,1345), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3671 {"evmwlumiaaw", VX (4,1352), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3673 {"evmwlsmiaaw", VX (4,1353), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3676 {"evmwssfaa", VX (4,1363), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3677 {"macchwo", XO (4, 172,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3678 {"evmwumiaa", VX (4,1368), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3679 {"macchwo.", XO (4, 172,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3680 {"evmwsmiaa", VX (4,1369), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3681 {"evmwsmfaa", VX (4,1371), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3682 {"nmacchwo", XO (4, 174,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3683 {"nmacchwo.", XO (4, 174,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3684 {"evmheusianw", VX (4,1408), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3686 {"evmhessianw", VX (4,1409), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3695 {"evmhessfanw", VX (4,1411), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3697 {"evmhousianw", VX (4,1412), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3698 {"evmhossianw", VX (4,1413), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3702 {"evmhossfanw", VX (4,1415), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3703 {"evmheumianw", VX (4,1416), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3704 {"evmhesmianw", VX (4,1417), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3705 {"evmhesmfanw", VX (4,1419), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3706 {"evmhoumianw", VX (4,1420), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3707 {"evmhosmianw", VX (4,1421), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3708 {"evmhosmfanw", VX (4,1423), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3709 {"macchwsuo", XO (4, 204,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3710 {"macchwsuo.", XO (4, 204,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3711 {"evmhegumian", VX (4,1448), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3712 {"evmhegsmian", VX (4,1449), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3713 {"evmhegsmfan", VX (4,1451), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3714 {"evmhogumian", VX (4,1452), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3715 {"evmhogsmian", VX (4,1453), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3716 {"evmhogsmfan", VX (4,1455), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3717 {"evmwlusianw", VX (4,1472), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3719 {"evmwlssianw", VX (4,1473), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3725 {"evmwlumianw", VX (4,1480), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3726 {"evmwlsmianw", VX (4,1481), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3729 {"evmwssfan", VX (4,1491), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3730 {"macchwso", XO (4, 236,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3731 {"evmwumian", VX (4,1496), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3732 {"macchwso.", XO (4, 236,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3733 {"evmwsmian", VX (4,1497), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3734 {"evmwsmfan", VX (4,1499), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3735 {"nmacchwso", XO (4, 238,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3736 {"nmacchwso.", XO (4, 238,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3793 {"maclhwuo", XO (4, 396,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3794 {"maclhwuo.", XO (4, 396,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3803 {"maclhwo", XO (4, 428,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3804 {"maclhwo.", XO (4, 428,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3805 {"nmaclhwo", XO (4, 430,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3806 {"nmaclhwo.", XO (4, 430,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3816 {"maclhwsuo", XO (4, 460,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3817 {"maclhwsuo.", XO (4, 460,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3824 {"maclhwso", XO (4, 492,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3825 {"maclhwso.", XO (4, 492,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3826 {"nmaclhwso", XO (4, 494,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3827 {"nmaclhwso.", XO (4, 494,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3828 {"dcbz_l", X (4,1014), XRT_MASK, PPCPS, 0, {RA, RB}},
4607 {"rlmi", M(22,0), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}},
4608 {"rlmi.", M(22,1), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}},
4610 {"rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, RB}},
4611 {"rlwnm", M(23,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
4612 {"rlnm", M(23,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
4613 {"rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, RB}},
4614 {"rlwnm.", M(23,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
4615 {"rlnm.", M(23,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
4653 {"rotld", MDS(30,8,0), MDSMB_MASK, PPC64, PPCVLE, {RA, RS, RB}},
4654 {"rldcl", MDS(30,8,0), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, MB6}},
4655 {"rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, PPCVLE, {RA, RS, RB}},
4656 {"rldcl.", MDS(30,8,1), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, MB6}},
4658 {"rldcr", MDS(30,9,0), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, ME6}},
4659 {"rldcr.", MDS(30,9,1), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, ME6}},
4661 {"cmpw", XOPL(31,0,0), XCMPL_MASK, PPCCOM, 0, {OBF, RA, RB}},
4662 {"cmpd", XOPL(31,0,1), XCMPL_MASK, PPC64, 0, {OBF, RA, RB}},
4663 {"cmp", X(31,0), XCMP_MASK, PPC, 0, {BF, L32OPT, RA, RB}},
4664 {"cmp", X(31,0), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}},
4666 {"twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, 0, {RA, RB}},
4667 {"tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, 0, {RA, RB}},
4668 {"twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, 0, {RA, RB}},
4669 {"tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, 0, {RA, RB}},
4670 {"tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, 0, {RA, RB}},
4671 {"teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, 0, {RA, RB}},
4672 {"twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, 0, {RA, RB}},
4673 {"tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, 0, {RA, RB}},
4674 {"twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, 0, {RA, RB}},
4675 {"tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, 0, {RA, RB}},
4676 {"twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, 0, {RA, RB}},
4677 {"tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, 0, {RA, RB}},
4678 {"twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, 0, {RA, RB}},
4679 {"tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, 0, {RA, RB}},
4680 {"twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, 0, {RA, RB}},
4681 {"tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, 0, {RA, RB}},
4682 {"twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, 0, {RA, RB}},
4683 {"tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, 0, {RA, RB}},
4684 {"twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, 0, {RA, RB}},
4685 {"tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, 0, {RA, RB}},
4686 {"twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, 0, {RA, RB}},
4687 {"tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, 0, {RA, RB}},
4688 {"twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, 0, {RA, RB}},
4689 {"tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, 0, {RA, RB}},
4690 {"twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, 0, {RA, RB}},
4691 {"tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, 0, {RA, RB}},
4692 {"twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, 0, {RA, RB}},
4693 {"tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, 0, {RA, RB}},
4695 {"twu", XTO(31,4,TOU), XTO_MASK, PPCCOM, 0, {RA, RB}},
4696 {"tu", XTO(31,4,TOU), XTO_MASK, PWRCOM, 0, {RA, RB}},
4697 {"tw", X(31,4), X_MASK, PPCCOM, 0, {TO, RA, RB}},
4698 {"t", X(31,4), X_MASK, PWRCOM, 0, {TO, RA, RB}},
4700 {"lvsl", X(31,6), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
4701 {"lvebx", X(31,7), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
4702 {"lbfcmx", APU(31,7,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
4704 {"subfc", XO(31,8,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4705 {"sf", XO(31,8,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4706 {"subc", XO(31,8,0,0), XO_MASK, PPCCOM, 0, {RT, RB, RA}},
4707 {"subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4708 {"sf.", XO(31,8,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4709 {"subc.", XO(31,8,0,1), XO_MASK, PPCCOM, 0, {RT, RB, RA}},
4711 {"mulhdu", XO(31,9,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
4712 {"mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
4714 {"addc", XO(31,10,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4715 {"a", XO(31,10,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4716 {"addc.", XO(31,10,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4717 {"a.", XO(31,10,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4719 {"mulhwu", XO(31,11,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
4720 {"mulhwu.", XO(31,11,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
4722 {"lxsiwzx", X(31,12), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}},
4724 {"isellt", X(31,15), X_MASK, PPCISEL, 0, {RT, RA0, RB}},
4728 {"tlbilxva", XTO(31,18,3), XTO_MASK, E500MC|PPCA2, 0, {RA0, RB}},
4729 {"tlbilx", X(31,18), X_MASK, E500MC|PPCA2, 0, {T, RA0, RB}},
4734 {"lwarx", X(31,20), XEH_MASK, PPC, 0, {RT, RA0, RB, EH}},
4736 {"ldx", X(31,21), X_MASK, PPC64, 0, {RT, RA0, RB}},
4738 {"icbt", X(31,22), X_MASK, BOOKE|PPCE300|PPCA2|PPC476, 0, {CT, RA0, RB}},
4740 {"lwzx", X(31,23), X_MASK, PPCCOM, 0, {RT, RA0, RB}},
4741 {"lx", X(31,23), X_MASK, PWRCOM, 0, {RT, RA, RB}},
4743 {"slw", XRC(31,24,0), X_MASK, PPCCOM, 0, {RA, RS, RB}},
4744 {"sl", XRC(31,24,0), X_MASK, PWRCOM, 0, {RA, RS, RB}},
4745 {"slw.", XRC(31,24,1), X_MASK, PPCCOM, 0, {RA, RS, RB}},
4746 {"sl.", XRC(31,24,1), X_MASK, PWRCOM, 0, {RA, RS, RB}},
4753 {"sld", XRC(31,27,0), X_MASK, PPC64, 0, {RA, RS, RB}},
4754 {"sld.", XRC(31,27,1), X_MASK, PPC64, 0, {RA, RS, RB}},
4756 {"and", XRC(31,28,0), X_MASK, COM, 0, {RA, RS, RB}},
4757 {"and.", XRC(31,28,1), X_MASK, COM, 0, {RA, RS, RB}},
4759 {"maskg", XRC(31,29,0), X_MASK, M601, PPCA2, {RA, RS, RB}},
4760 {"maskg.", XRC(31,29,1), X_MASK, M601, PPCA2, {RA, RS, RB}},
4762 {"ldepx", X(31,29), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
4767 {"lwepx", X(31,31), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
4769 {"cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM, 0, {OBF, RA, RB}},
4770 {"cmpld", XOPL(31,32,1), XCMPL_MASK, PPC64, 0, {OBF, RA, RB}},
4771 {"cmpl", X(31,32), XCMP_MASK, PPC, 0, {BF, L32OPT, RA, RB}},
4772 {"cmpl", X(31,32), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}},
4774 {"lvsr", X(31,38), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
4775 {"lvehx", X(31,39), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
4776 {"lhfcmx", APU(31,39,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
4778 {"mviwsplt", X(31,46), X_MASK, PPCVEC2, 0, {VD, RA, RB}},
4780 {"iselgt", X(31,47), X_MASK, PPCISEL, 0, {RT, RA0, RB}},
4782 {"lvewx", X(31,71), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
4784 {"addg6s", XO(31,74,0,0), XO_MASK, POWER6, 0, {RT, RA, RB}},
4786 {"lxsiwax", X(31,76), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}},
4788 {"iseleq", X(31,79), X_MASK, PPCISEL, 0, {RT, RA0, RB}},
4790 {"isel", XISEL(31,15), XISEL_MASK, PPCISEL|TITAN, 0, {RT, RA0, RB, CRB}},
4792 {"subf", XO(31,40,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
4793 {"sub", XO(31,40,0,0), XO_MASK, PPC, 0, {RT, RB, RA}},
4794 {"subf.", XO(31,40,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
4795 {"sub.", XO(31,40,0,1), XO_MASK, PPC, 0, {RT, RB, RA}},
4800 {"eratilx", X(31,51), X_MASK, PPCA2, 0, {ERAT_T, RA, RB}},
4802 {"lbarx", X(31,52), XEH_MASK, POWER8|E6500, 0, {RT, RA0, RB, EH}},
4804 {"ldux", X(31,53), X_MASK, PPC64, 0, {RT, RAL, RB}},
4806 {"dcbst", X(31,54), XRT_MASK, PPC, 0, {RA0, RB}},
4808 {"lwzux", X(31,55), X_MASK, PPCCOM, 0, {RT, RAL, RB}},
4809 {"lux", X(31,55), X_MASK, PWRCOM, 0, {RT, RA, RB}},
4814 {"andc", XRC(31,60,0), X_MASK, COM, 0, {RA, RS, RB}},
4815 {"andc.", XRC(31,60,1), X_MASK, COM, 0, {RA, RS, RB}},
4821 {"dcbstep", XRT(31,63,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}},
4823 {"tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, 0, {RA, RB}},
4824 {"tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, 0, {RA, RB}},
4825 {"tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, 0, {RA, RB}},
4826 {"tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, 0, {RA, RB}},
4827 {"tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, 0, {RA, RB}},
4828 {"tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, 0, {RA, RB}},
4829 {"tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, 0, {RA, RB}},
4830 {"tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, 0, {RA, RB}},
4831 {"tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, 0, {RA, RB}},
4832 {"tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, 0, {RA, RB}},
4833 {"tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, 0, {RA, RB}},
4834 {"tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, 0, {RA, RB}},
4835 {"tdng", XTO(31,68,TONG), XTO_MASK, PPC64, 0, {RA, RB}},
4836 {"tdne", XTO(31,68,TONE), XTO_MASK, PPC64, 0, {RA, RB}},
4837 {"tdu", XTO(31,68,TOU), XTO_MASK, PPC64, 0, {RA, RB}},
4838 {"td", X(31,68), X_MASK, PPC64, 0, {TO, RA, RB}},
4840 {"lwfcmx", APU(31,71,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
4841 {"mulhd", XO(31,73,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
4842 {"mulhd.", XO(31,73,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
4844 {"mulhw", XO(31,75,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
4845 {"mulhw.", XO(31,75,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
4847 {"dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440|TITAN, 0, {RA, RS, RB}},
4848 {"dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440|TITAN, 0, {RA, RS, RB}},
4854 {"ldarx", X(31,84), XEH_MASK, PPC64, 0, {RT, RA0, RB, EH}},
4856 {"dcbfl", XOPL(31,86,1), XRT_MASK, POWER5, PPC476, {RA0, RB}},
4857 {"dcbf", X(31,86), XLRT_MASK, PPC, 0, {RA0, RB, L2OPT}},
4859 {"lbzx", X(31,87), X_MASK, COM, 0, {RT, RA0, RB}},
4861 {"lbepx", X(31,95), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
4865 {"lvx", X(31,103), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
4866 {"lqfcmx", APU(31,103,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
4871 {"mul", XO(31,107,0,0), XO_MASK, M601, 0, {RT, RA, RB}},
4872 {"mul.", XO(31,107,0,1), XO_MASK, M601, 0, {RT, RA, RB}},
4874 {"mvidsplt", X(31,110), X_MASK, PPCVEC2, 0, {VD, RA, RB}},
4876 {"mtsrdin", X(31,114), XRA_MASK, PPC64, 0, {RS, RB}},
4882 {"lharx", X(31,116), XEH_MASK, POWER8|E6500, 0, {RT, RA0, RB, EH}},
4884 {"clf", X(31,118), XTO_MASK, POWER, 0, {RA, RB}},
4886 {"lbzux", X(31,119), X_MASK, COM, 0, {RT, RAL, RB}},
4891 {"nor", XRC(31,124,0), X_MASK, COM, 0, {RA, RS, RB}},
4893 {"nor.", XRC(31,124,1), X_MASK, COM, 0, {RA, RS, RB}},
4895 {"dcbfep", XRT(31,127,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}},
4901 {"dcbtstls", X(31,134), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
4903 {"stvebx", X(31,135), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
4904 {"stbfcmx", APU(31,135,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
4906 {"subfe", XO(31,136,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4907 {"sfe", XO(31,136,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4908 {"subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4909 {"sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4911 {"adde", XO(31,138,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4912 {"ae", XO(31,138,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4913 {"adde.", XO(31,138,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4914 {"ae.", XO(31,138,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4916 {"stxsiwx", X(31,140), XX1_MASK, PPCVSX2, 0, {XS6, RA0, RB}},
4918 {"msgsndp", XRTRA(31,142,0,0), XRTRA_MASK, POWER8, 0, {RB}},
4919 {"dcbtstlse", X(31,142), X_MASK, PPCCHLK, E500MC, {CT, RA0, RB}},
4929 {"eratsx", XRC(31,147,0), X_MASK, PPCA2, 0, {RT, RA0, RB}},
4930 {"eratsx.", XRC(31,147,1), X_MASK, PPCA2, 0, {RT, RA0, RB}},
4932 {"stdx", X(31,149), X_MASK, PPC64, 0, {RS, RA0, RB}},
4934 {"stwcx.", XRC(31,150,1), X_MASK, PPC, 0, {RS, RA0, RB}},
4936 {"stwx", X(31,151), X_MASK, PPCCOM, 0, {RS, RA0, RB}},
4937 {"stx", X(31,151), X_MASK, PWRCOM, 0, {RS, RA, RB}},
4939 {"slq", XRC(31,152,0), X_MASK, M601, 0, {RA, RS, RB}},
4940 {"slq.", XRC(31,152,1), X_MASK, M601, 0, {RA, RS, RB}},
4942 {"sle", XRC(31,153,0), X_MASK, M601, 0, {RA, RS, RB}},
4943 {"sle.", XRC(31,153,1), X_MASK, M601, 0, {RA, RS, RB}},
4947 {"stdepx", X(31,157), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
4949 {"stwepx", X(31,159), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
4953 {"dcbtls", X(31,166), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
4955 {"stvehx", X(31,167), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
4956 {"sthfcmx", APU(31,167,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
4958 {"addex", ZRC(31,170,0), Z2_MASK, POWER9, 0, {RT, RA, RB, CY}},
4960 {"msgclrp", XRTRA(31,174,0,0), XRTRA_MASK, POWER8, 0, {RB}},
4961 {"dcbtlse", X(31,174), X_MASK, PPCCHLK, E500MC, {CT, RA0, RB}},
4970 {"stdux", X(31,181), X_MASK, PPC64, 0, {RS, RAS, RB}},
4972 {"stqcx.", XRC(31,182,1), X_MASK, POWER8, 0, {RSQ, RA0, RB}},
4975 {"stwux", X(31,183), X_MASK, PPCCOM, 0, {RS, RAS, RB}},
4976 {"stux", X(31,183), X_MASK, PWRCOM, 0, {RS, RA0, RB}},
4983 {"cmprb", X(31,192), XCMP_MASK, POWER9, 0, {BF, L, RA, RB}},
4985 {"icblq.", XRC(31,198,1), X_MASK, E6500, 0, {CT, RA0, RB}},
4987 {"stvewx", X(31,199), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
4988 {"stwfcmx", APU(31,199,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
5000 {"msgsnd", XRTRA(31,206,0,0), XRTRA_MASK, E500MC|PPCA2|POWER8, 0, {RB}},
5009 {"ldawx.", XRC(31,212,1), X_MASK, PPCA2, 0, {RT, RA0, RB}},
5011 {"stdcx.", XRC(31,214,1), X_MASK, PPC64, 0, {RS, RA0, RB}},
5013 {"stbx", X(31,215), X_MASK, COM, 0, {RS, RA0, RB}},
5015 {"sllq", XRC(31,216,0), X_MASK, M601, 0, {RA, RS, RB}},
5016 {"sllq.", XRC(31,216,1), X_MASK, M601, 0, {RA, RS, RB}},
5018 {"sleq", XRC(31,217,0), X_MASK, M601, 0, {RA, RS, RB}},
5019 {"sleq.", XRC(31,217,1), X_MASK, M601, 0, {RA, RS, RB}},
5021 {"stbepx", X(31,223), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
5023 {"cmpeqb", X(31,224), XCMPL_MASK, POWER9, 0, {BF, RA, RB}},
5025 {"icblc", X(31,230), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
5027 {"stvx", X(31,231), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
5028 {"stqfcmx", APU(31,231,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
5035 {"mulld", XO(31,233,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
5036 {"mulld.", XO(31,233,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
5043 {"mullw", XO(31,235,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5044 {"muls", XO(31,235,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5045 {"mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5046 {"muls.", XO(31,235,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5048 {"icblce", X(31,238), X_MASK, PPCCHLK, E500MC|PPCA2, {CT, RA, RB}},
5049 {"msgclr", XRTRA(31,238,0,0), XRTRA_MASK, E500MC|PPCA2|POWER8, 0, {RB}},
5050 {"mtsrin", X(31,242), XRA_MASK, PPC, NON32, {RS, RB}},
5051 {"mtsri", X(31,242), XRA_MASK, POWER, NON32, {RS, RB}},
5057 {"dcbtstt", XRT(31,246,0x10), XRT_MASK, POWER7, 0, {RA0, RB}},
5058 {"dcbtst", X(31,246), X_MASK, POWER4, DCBT_EO, {RA0, RB, CT}},
5059 {"dcbtst", X(31,246), X_MASK, DCBT_EO, 0, {CT, RA0, RB}},
5060 {"dcbtst", X(31,246), X_MASK, PPC, POWER4|DCBT_EO, {RA0, RB}},
5062 {"stbux", X(31,247), X_MASK, COM, 0, {RS, RAS, RB}},
5067 {"bpermd", X(31,252), X_MASK, POWER7|PPCA2, 0, {RA, RS, RB}},
5069 {"dcbtstep", XRT(31,255,0), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
5074 {"lvexbx", X(31,261), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
5076 {"icbt", X(31,262), XRT_MASK, PPC403, 0, {RA, RB}},
5078 {"lvepxl", X(31,263), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
5080 {"ldfcmx", APU(31,263,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
5081 {"doz", XO(31,264,0,0), XO_MASK, M601, 0, {RT, RA, RB}},
5082 {"doz.", XO(31,264,0,1), XO_MASK, M601, 0, {RT, RA, RB}},
5084 {"modud", X(31,265), X_MASK, POWER9, 0, {RT, RA, RB}},
5086 {"add", XO(31,266,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5087 {"cax", XO(31,266,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5088 {"add.", XO(31,266,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5089 {"cax.", XO(31,266,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5091 {"moduw", X(31,267), X_MASK, POWER9, 0, {RT, RA, RB}},
5093 {"lxvx", X(31,268), XX1_MASK|1<<6, PPCVSX3, 0, {XT6, RA0, RB}},
5094 {"lxvl", X(31,269), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
5098 {"tlbiel", X(31,274), X_MASK|1<<20,POWER9, PPC476, {RB, RSO, RIC, PRS, X_R}},
5099 {"tlbiel", X(31,274), XRTLRA_MASK, POWER4, POWER9|PPC476, {RB, LOPT}},
5105 {"lscbx", XRC(31,277,0), X_MASK, M601, 0, {RT, RA, RB}},
5106 {"lscbx.", XRC(31,277,1), X_MASK, M601, 0, {RT, RA, RB}},
5108 {"dcbtt", XRT(31,278,0x10), XRT_MASK, POWER7, 0, {RA0, RB}},
5109 {"dcbt", X(31,278), X_MASK, POWER4, DCBT_EO, {RA0, RB, CT}},
5110 {"dcbt", X(31,278), X_MASK, DCBT_EO, 0, {CT, RA0, RB}},
5111 {"dcbt", X(31,278), X_MASK, PPC, POWER4|DCBT_EO, {RA0, RB}},
5113 {"lhzx", X(31,279), X_MASK, COM, 0, {RT, RA0, RB}},
5117 {"eqv", XRC(31,284,0), X_MASK, COM, 0, {RA, RS, RB}},
5118 {"eqv.", XRC(31,284,1), X_MASK, COM, 0, {RA, RS, RB}},
5120 {"lhepx", X(31,287), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
5124 {"lvexhx", X(31,293), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
5125 {"lvepx", X(31,295), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
5127 {"lxvll", X(31,301), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
5131 {"tlbie", X(31,306), X_MASK|1<<20,POWER9, TITAN, {RB, RS, RIC, PRS, X_R}},
5132 {"tlbie", X(31,306), XRA_MASK, POWER7, POWER9|TITAN, {RB, RS}},
5133 {"tlbie", X(31,306), XRTLRA_MASK, PPC, E500|POWER7|TITAN, {RB, LOPT}},
5134 {"tlbi", X(31,306), XRT_MASK, POWER, 0, {RA0, RB}},
5138 {"ldmx", X(31,309), X_MASK, POWER9, 0, {RT, RA0, RB}},
5140 {"eciwx", X(31,310), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}},
5142 {"lhzux", X(31,311), X_MASK, COM, 0, {RT, RAL, RB}},
5146 {"xor", XRC(31,316,0), X_MASK, COM, 0, {RA, RS, RB}},
5147 {"xor.", XRC(31,316,1), X_MASK, COM, 0, {RA, RS, RB}},
5149 {"dcbtep", XRT(31,319,0), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
5188 {"lvexwx", X(31,325), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
5190 {"dcread", X(31,326), X_MASK, PPC476|TITAN, 0, {RT, RA0, RB}},
5192 {"div", XO(31,331,0,0), XO_MASK, M601, 0, {RT, RA, RB}},
5193 {"div.", XO(31,331,0,1), XO_MASK, M601, 0, {RT, RA, RB}},
5195 {"lxvdsx", X(31,332), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}},
5404 {"lwax", X(31,341), X_MASK, PPC64, 0, {RT, RA0, RB}},
5406 {"dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}},
5408 {"lhax", X(31,343), X_MASK, COM, 0, {RT, RA0, RB}},
5410 {"lvxl", X(31,359), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
5415 {"divs", XO(31,363,0,0), XO_MASK, M601, 0, {RT, RA, RB}},
5416 {"divs.", XO(31,363,0,1), XO_MASK, M601, 0, {RT, RA, RB}},
5418 {"lxvwsx", X(31,364), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
5426 {"lwaux", X(31,373), X_MASK, PPC64, 0, {RT, RAL, RB}},
5428 {"dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}},
5430 {"lhaux", X(31,375), X_MASK, COM, 0, {RT, RAL, RB}},
5437 {"stvexbx", X(31,389), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
5439 {"dcblc", X(31,390), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
5440 {"stdfcmx", APU(31,391,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
5442 {"divdeu", XO(31,393,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5443 {"divdeu.", XO(31,393,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5444 {"divweu", XO(31,395,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5445 {"divweu.", XO(31,395,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5447 {"stxvx", X(31,396), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
5448 {"stxvl", X(31,397), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
5450 {"dcblce", X(31,398), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}},
5452 {"slbmte", X(31,402), XRA_MASK, PPC64, 0, {RS, RB}},
5456 {"pbt.", XRC(31,404,1), X_MASK, POWER8, 0, {RS, RA0, RB}},
5458 {"icswx", XRC(31,406,0), X_MASK, POWER7|PPCA2, 0, {RS, RA, RB}},
5459 {"icswx.", XRC(31,406,1), X_MASK, POWER7|PPCA2, 0, {RS, RA, RB}},
5461 {"sthx", X(31,407), X_MASK, COM, 0, {RS, RA0, RB}},
5463 {"orc", XRC(31,412,0), X_MASK, COM, 0, {RA, RS, RB}},
5464 {"orc.", XRC(31,412,1), X_MASK, COM, 0, {RA, RS, RB}},
5466 {"sthepx", X(31,415), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
5470 {"stvexhx", X(31,421), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
5472 {"dcblq.", XRC(31,422,1), X_MASK, E6500, 0, {CT, RA0, RB}},
5474 {"divde", XO(31,425,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5475 {"divde.", XO(31,425,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5476 {"divwe", XO(31,427,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5477 {"divwe.", XO(31,427,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5479 {"stxvll", X(31,429), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
5483 {"slbie", X(31,434), XRTRA_MASK, PPC64, 0, {RB}},
5485 {"mtvsrdd", X(31,435), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
5487 {"ecowx", X(31,438), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}},
5489 {"sthux", X(31,439), X_MASK, COM, 0, {RS, RAS, RB}},
5501 {"or", XRC(31,444,0), X_MASK, COM, 0, {RA, RS, RB}},
5503 {"or.", XRC(31,444,1), X_MASK, COM, 0, {RA, RS, RB}},
5542 {"stvexwx", X(31,453), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
5547 {"divdu", XO(31,457,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
5548 {"divdu.", XO(31,457,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
5550 {"divwu", XO(31,459,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
5551 {"divwu.", XO(31,459,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
5556 {"slbieg", X(31,466), XRA_MASK, POWER9, 0, {RS, RB}},
5724 {"dcbi", X(31,470), XRT_MASK, PPC, 0, {RA0, RB}},
5726 {"nand", XRC(31,476,0), X_MASK, COM, 0, {RA, RS, RB}},
5727 {"nand.", XRC(31,476,1), X_MASK, COM, 0, {RA, RS, RB}},
5729 {"dsn", X(31,483), XRT_MASK, E500MC, 0, {RA, RB}},
5731 {"dcread", X(31,486), X_MASK, PPC403|PPC440, PPCA2|PPC476, {RT, RA0, RB}},
5733 {"icbtls", X(31,486), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
5735 {"stvxl", X(31,487), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
5740 {"divd", XO(31,489,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
5741 {"divd.", XO(31,489,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
5743 {"divw", XO(31,491,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
5744 {"divw.", XO(31,491,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
5746 {"icbtlse", X(31,494), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}},
5755 {"cmpb", X(31,508), X_MASK, POWER6|PPCA2|PPC476, 0, {RA, RS, RB}},
5759 {"lbdcbx", X(31,514), X_MASK, E200Z4, 0, {RT, RA, RB}},
5760 {"lbdx", X(31,515), X_MASK, E500MC, 0, {RT, RA, RB}},
5764 {"lvlx", X(31,519), X_MASK, CELL, 0, {VD, RA0, RB}},
5765 {"lbfcmux", APU(31,519,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
5767 {"subfco", XO(31,8,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5768 {"sfo", XO(31,8,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5769 {"subco", XO(31,8,1,0), XO_MASK, PPCCOM, 0, {RT, RB, RA}},
5770 {"subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5771 {"sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5772 {"subco.", XO(31,8,1,1), XO_MASK, PPCCOM, 0, {RT, RB, RA}},
5774 {"addco", XO(31,10,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5775 {"ao", XO(31,10,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5776 {"addco.", XO(31,10,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5777 {"ao.", XO(31,10,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5779 {"lxsspx", X(31,524), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}},
5783 {"ldbrx", X(31,532), X_MASK, CELL|POWER7|PPCA2, 0, {RT, RA0, RB}},
5786 {"lsx", X(31,533), X_MASK, PWRCOM, 0, {RT, RA, RB}},
5788 {"lwbrx", X(31,534), X_MASK, PPCCOM, 0, {RT, RA0, RB}},
5789 {"lbrx", X(31,534), X_MASK, PWRCOM, 0, {RT, RA, RB}},
5791 {"lfsx", X(31,535), X_MASK, COM, PPCEFS, {FRT, RA0, RB}},
5793 {"srw", XRC(31,536,0), X_MASK, PPCCOM, 0, {RA, RS, RB}},
5794 {"sr", XRC(31,536,0), X_MASK, PWRCOM, 0, {RA, RS, RB}},
5795 {"srw.", XRC(31,536,1), X_MASK, PPCCOM, 0, {RA, RS, RB}},
5796 {"sr.", XRC(31,536,1), X_MASK, PWRCOM, 0, {RA, RS, RB}},
5798 {"rrib", XRC(31,537,0), X_MASK, M601, 0, {RA, RS, RB}},
5799 {"rrib.", XRC(31,537,1), X_MASK, M601, 0, {RA, RS, RB}},
5804 {"srd", XRC(31,539,0), X_MASK, PPC64, 0, {RA, RS, RB}},
5805 {"srd.", XRC(31,539,1), X_MASK, PPC64, 0, {RA, RS, RB}},
5807 {"maskir", XRC(31,541,0), X_MASK, M601, 0, {RA, RS, RB}},
5808 {"maskir.", XRC(31,541,1), X_MASK, M601, 0, {RA, RS, RB}},
5810 {"lhdcbx", X(31,546), X_MASK, E200Z4, 0, {RT, RA, RB}},
5811 {"lhdx", X(31,547), X_MASK, E500MC, 0, {RT, RA, RB}},
5813 {"lvtrx", X(31,549), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
5817 {"lvrx", X(31,551), X_MASK, CELL, 0, {VD, RA0, RB}},
5818 {"lhfcmux", APU(31,551,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
5820 {"subfo", XO(31,40,1,0), XO_MASK, PPC, 0, {RT, RA, RB}},
5821 {"subo", XO(31,40,1,0), XO_MASK, PPC, 0, {RT, RB, RA}},
5822 {"subfo.", XO(31,40,1,1), XO_MASK, PPC, 0, {RT, RA, RB}},
5823 {"subo.", XO(31,40,1,1), XO_MASK, PPC, 0, {RT, RB, RA}},
5827 {"lfsux", X(31,567), X_MASK, COM, PPCEFS, {FRT, RAS, RB}},
5834 {"lwdcbx", X(31,578), X_MASK, E200Z4, 0, {RT, RA, RB}},
5835 {"lwdx", X(31,579), X_MASK, E500MC, 0, {RT, RA, RB}},
5837 {"lvtlx", X(31,581), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
5841 {"lwfcmux", APU(31,583,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
5843 {"lxsdx", X(31,588), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}},
5860 {"lfdx", X(31,599), X_MASK, COM, PPCEFS, {FRT, RA0, RB}},
5862 {"mffgpr", XRC(31,607,0), XRA_MASK, POWER6, POWER7, {FRT, RB}},
5863 {"lfdepx", X(31,607), X_MASK, E500MC|PPCA2, 0, {FRT, RA0, RB}},
5865 {"lddx", X(31,611), X_MASK, E500MC, 0, {RT, RA, RB}},
5867 {"lvswx", X(31,613), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
5871 {"lqfcmux", APU(31,615,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
5876 {"mulo", XO(31,107,1,0), XO_MASK, M601, 0, {RT, RA, RB}},
5877 {"mulo.", XO(31,107,1,1), XO_MASK, M601, 0, {RT, RA, RB}},
5879 {"mfsri", X(31,627), X_MASK, M601, 0, {RT, RA, RB}},
5883 {"lfdux", X(31,631), X_MASK, COM, PPCEFS, {FRT, RAS, RB}},
5885 {"stbdcbx", X(31,642), X_MASK, E200Z4, 0, {RS, RA, RB}},
5886 {"stbdx", X(31,643), X_MASK, E500MC, 0, {RS, RA, RB}},
5888 {"stvlx", X(31,647), X_MASK, CELL, 0, {VS, RA0, RB}},
5889 {"stbfcmux", APU(31,647,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
5891 {"stxsspx", X(31,652), XX1_MASK, PPCVSX2, 0, {XS6, RA0, RB}},
5895 {"subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5896 {"sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5897 {"subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5898 {"sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5900 {"addeo", XO(31,138,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5901 {"aeo", XO(31,138,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5902 {"addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5903 {"aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5905 {"mfsrin", X(31,659), XRA_MASK, PPC, NON32, {RT, RB}},
5907 {"stdbrx", X(31,660), X_MASK, CELL|POWER7|PPCA2, 0, {RS, RA0, RB}},
5909 {"stswx", X(31,661), X_MASK, PPCCOM, E500|E500MC, {RS, RA0, RB}},
5910 {"stsx", X(31,661), X_MASK, PWRCOM, 0, {RS, RA0, RB}},
5912 {"stwbrx", X(31,662), X_MASK, PPCCOM, 0, {RS, RA0, RB}},
5913 {"stbrx", X(31,662), X_MASK, PWRCOM, 0, {RS, RA0, RB}},
5915 {"stfsx", X(31,663), X_MASK, COM, PPCEFS, {FRS, RA0, RB}},
5917 {"srq", XRC(31,664,0), X_MASK, M601, 0, {RA, RS, RB}},
5918 {"srq.", XRC(31,664,1), X_MASK, M601, 0, {RA, RS, RB}},
5920 {"sre", XRC(31,665,0), X_MASK, M601, 0, {RA, RS, RB}},
5921 {"sre.", XRC(31,665,1), X_MASK, M601, 0, {RA, RS, RB}},
5923 {"sthdcbx", X(31,674), X_MASK, E200Z4, 0, {RS, RA, RB}},
5924 {"sthdx", X(31,675), X_MASK, E500MC, 0, {RS, RA, RB}},
5926 {"stvfrx", X(31,677), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
5928 {"stvrx", X(31,679), X_MASK, CELL, 0, {VS, RA0, RB}},
5929 {"sthfcmux", APU(31,679,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
5934 {"stbcx.", XRC(31,694,1), X_MASK, POWER8|E6500, 0, {RS, RA0, RB}},
5936 {"stfsux", X(31,695), X_MASK, COM, PPCEFS, {FRS, RAS, RB}},
5941 {"stwdcbx", X(31,706), X_MASK, E200Z4, 0, {RS, RA, RB}},
5942 {"stwdx", X(31,707), X_MASK, E500MC, 0, {RS, RA, RB}},
5944 {"stvflx", X(31,709), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
5948 {"stwfcmux", APU(31,711,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
5950 {"stxsdx", X(31,716), XX1_MASK, PPCVSX, 0, {XS6, RA0, RB}},
5967 {"sthcx.", XRC(31,726,1), X_MASK, POWER8|E6500, 0, {RS, RA0, RB}},
5969 {"stfdx", X(31,727), X_MASK, COM, PPCEFS, {FRS, RA0, RB}},
5971 {"srlq", XRC(31,728,0), X_MASK, M601, 0, {RA, RS, RB}},
5972 {"srlq.", XRC(31,728,1), X_MASK, M601, 0, {RA, RS, RB}},
5974 {"sreq", XRC(31,729,0), X_MASK, M601, 0, {RA, RS, RB}},
5975 {"sreq.", XRC(31,729,1), X_MASK, M601, 0, {RA, RS, RB}},
5978 {"stfdepx", X(31,735), X_MASK, E500MC|PPCA2, 0, {FRS, RA0, RB}},
5980 {"stddx", X(31,739), X_MASK, E500MC, 0, {RS, RA, RB}},
5982 {"stvswx", X(31,741), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
5986 {"stqfcmux", APU(31,743,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
5993 {"mulldo", XO(31,233,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
5994 {"mulldo.", XO(31,233,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
6001 {"mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
6002 {"mulso", XO(31,235,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
6003 {"mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
6004 {"mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
6012 {"dcba", X(31,758), XRT_MASK, PPC405|PPC7450|BOOKE|PPCA2|PPC476, 0, {RA0, RB}},
6013 {"dcbal", XOPL(31,758,1), XRT_MASK, E500MC, 0, {RA0, RB}},
6015 {"stfdux", X(31,759), X_MASK, COM, PPCEFS, {FRS, RAS, RB}},
6020 {"lvsm", X(31,773), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
6022 {"copy", XOPL(31,774,1), XRT_MASK, POWER9, 0, {RA0, RB}},
6024 {"stvepxl", X(31,775), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
6025 {"lvlxl", X(31,775), X_MASK, CELL, 0, {VD, RA0, RB}},
6026 {"ldfcmux", APU(31,775,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
6028 {"dozo", XO(31,264,1,0), XO_MASK, M601, 0, {RT, RA, RB}},
6029 {"dozo.", XO(31,264,1,1), XO_MASK, M601, 0, {RT, RA, RB}},
6031 {"addo", XO(31,266,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
6032 {"caxo", XO(31,266,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
6033 {"addo.", XO(31,266,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
6034 {"caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
6036 {"modsd", X(31,777), X_MASK, POWER9, 0, {RT, RA, RB}},
6037 {"modsw", X(31,779), X_MASK, POWER9, 0, {RT, RA, RB}},
6039 {"lxvw4x", X(31,780), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}},
6040 {"lxsibzx", X(31,781), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
6042 {"tabortwc.", XRC(31,782,1), X_MASK, PPCHTM, 0, {TO, RA, RB}},
6044 {"tlbivax", X(31,786), XRT_MASK, BOOKE|PPCA2|PPC476, 0, {RA0, RB}},
6046 {"lwzcix", X(31,789), X_MASK, POWER6, 0, {RT, RA0, RB}},
6048 {"lhbrx", X(31,790), X_MASK, COM, 0, {RT, RA0, RB}},
6050 {"lfdpx", X(31,791), X_MASK, POWER6, POWER7, {FRTp, RA0, RB}},
6051 {"lfqx", X(31,791), X_MASK, POWER2, 0, {FRT, RA, RB}},
6053 {"sraw", XRC(31,792,0), X_MASK, PPCCOM, 0, {RA, RS, RB}},
6054 {"sra", XRC(31,792,0), X_MASK, PWRCOM, 0, {RA, RS, RB}},
6055 {"sraw.", XRC(31,792,1), X_MASK, PPCCOM, 0, {RA, RS, RB}},
6056 {"sra.", XRC(31,792,1), X_MASK, PWRCOM, 0, {RA, RS, RB}},
6058 {"srad", XRC(31,794,0), X_MASK, PPC64, 0, {RA, RS, RB}},
6059 {"srad.", XRC(31,794,1), X_MASK, PPC64, 0, {RA, RS, RB}},
6061 {"lfddx", X(31,803), X_MASK, E500MC, 0, {FRT, RA, RB}},
6063 {"lvtrxl", X(31,805), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
6064 {"stvepx", X(31,807), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
6065 {"lvrxl", X(31,807), X_MASK, CELL, 0, {VD, RA0, RB}},
6067 {"lxvh8x", X(31,812), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
6068 {"lxsihzx", X(31,813), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
6070 {"tabortdc.", XRC(31,814,1), X_MASK, PPCHTM, 0, {TO, RA, RB}},
6072 {"rac", X(31,818), X_MASK, M601, 0, {RT, RA, RB}},
6074 {"erativax", X(31,819), X_MASK, PPCA2, 0, {RS, RA0, RB}},
6076 {"lhzcix", X(31,821), X_MASK, POWER6, 0, {RT, RA0, RB}},
6080 {"lfqux", X(31,823), X_MASK, POWER2, 0, {FRT, RA, RB}},
6090 {"lvtlxl", X(31,837), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
6094 {"divo", XO(31,331,1,0), XO_MASK, M601, 0, {RT, RA, RB}},
6095 {"divo.", XO(31,331,1,1), XO_MASK, M601, 0, {RT, RA, RB}},
6097 {"lxvd2x", X(31,844), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}},
6098 {"lxvx", X(31,844), XX1_MASK, POWER8, POWER9|PPCVSX3, {XT6, RA0, RB}},
6102 {"tlbsrx.", XRC(31,850,1), XRT_MASK, PPCA2, 0, {RA0, RB}},
6105 {"slbmfev", X(31,851), XRLA_MASK, POWER9, 0, {RT, RB, A_L}},
6106 {"slbmfev", X(31,851), XRA_MASK, PPC64, POWER9, {RT, RB}},
6108 {"lbzcix", X(31,853), X_MASK, POWER6, 0, {RT, RA0, RB}},
6115 {"lfiwax", X(31,855), X_MASK, POWER6|PPCA2|PPC476, 0, {FRT, RA0, RB}},
6117 {"lvswxl", X(31,869), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
6122 {"divso", XO(31,363,1,0), XO_MASK, M601, 0, {RT, RA, RB}},
6123 {"divso.", XO(31,363,1,1), XO_MASK, M601, 0, {RT, RA, RB}},
6125 {"lxvb16x", X(31,876), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
6129 {"rmieg", X(31,882), XRTRA_MASK, POWER9, 0, {RB}},
6131 {"ldcix", X(31,885), X_MASK, POWER6, 0, {RT, RA0, RB}},
6135 {"lfiwzx", X(31,887), X_MASK, POWER7|PPCA2, 0, {FRT, RA0, RB}},
6140 {"paste.", XRCL(31,902,1,1),XRT_MASK, POWER9, 0, {RA0, RB}},
6142 {"stvlxl", X(31,903), X_MASK, CELL, 0, {VS, RA0, RB}},
6143 {"stdfcmux", APU(31,903,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
6145 {"divdeuo", XO(31,393,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6146 {"divdeuo.", XO(31,393,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6147 {"divweuo", XO(31,395,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6148 {"divweuo.", XO(31,395,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6150 {"stxvw4x", X(31,908), XX1_MASK, PPCVSX, 0, {XS6, RA0, RB}},
6151 {"stxsibx", X(31,909), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
6155 {"tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RTO, RA0, RB}},
6156 {"tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RTO, RA0, RB}},
6158 {"slbmfee", X(31,915), XRLA_MASK, POWER9, 0, {RT, RB, A_L}},
6159 {"slbmfee", X(31,915), XRA_MASK, PPC64, POWER9, {RT, RB}},
6161 {"stwcix", X(31,917), X_MASK, POWER6, 0, {RS, RA0, RB}},
6163 {"sthbrx", X(31,918), X_MASK, COM, 0, {RS, RA0, RB}},
6165 {"stfdpx", X(31,919), X_MASK, POWER6, POWER7, {FRSp, RA0, RB}},
6166 {"stfqx", X(31,919), X_MASK, POWER2, 0, {FRS, RA0, RB}},
6168 {"sraq", XRC(31,920,0), X_MASK, M601, 0, {RA, RS, RB}},
6169 {"sraq.", XRC(31,920,1), X_MASK, M601, 0, {RA, RS, RB}},
6171 {"srea", XRC(31,921,0), X_MASK, M601, 0, {RA, RS, RB}},
6172 {"srea.", XRC(31,921,1), X_MASK, M601, 0, {RA, RS, RB}},
6179 {"stfddx", X(31,931), X_MASK, E500MC, 0, {FRS, RA, RB}},
6181 {"stvfrxl", X(31,933), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
6183 {"wclrone", XOPL2(31,934,2),XRT_MASK, PPCA2, 0, {RA0, RB}},
6185 {"wclr", X(31,934), X_MASK, PPCA2, 0, {L2, RA0, RB}},
6187 {"stvrxl", X(31,935), X_MASK, CELL, 0, {VS, RA0, RB}},
6189 {"divdeo", XO(31,425,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6190 {"divdeo.", XO(31,425,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6191 {"divweo", XO(31,427,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6192 {"divweo.", XO(31,427,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6194 {"stxvh8x", X(31,940), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
6195 {"stxsihx", X(31,941), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
6203 {"sthcix", X(31,949), X_MASK, POWER6, 0, {RS, RA0, RB}},
6205 {"icswepx", XRC(31,950,0), X_MASK, PPCA2, 0, {RS, RA, RB}},
6206 {"icswepx.", XRC(31,950,1), X_MASK, PPCA2, 0, {RS, RA, RB}},
6208 {"stfqux", X(31,951), X_MASK, POWER2, 0, {FRS, RA, RB}},
6216 {"stvflxl", X(31,965), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
6221 {"divduo", XO(31,457,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
6222 {"divduo.", XO(31,457,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
6224 {"divwuo", XO(31,459,1,0), XO_MASK, PPC, 0, {RT, RA, RB}},
6225 {"divwuo.", XO(31,459,1,1), XO_MASK, PPC, 0, {RT, RA, RB}},
6227 {"stxvd2x", X(31,972), XX1_MASK, PPCVSX, 0, {XS6, RA0, RB}},
6228 {"stxvx", X(31,972), XX1_MASK, POWER8, POWER9|PPCVSX3, {XS6, RA0, RB}},
6230 {"tlbld", X(31,978), XRTRA_MASK, PPC, PPC403|BOOKE|PPCA2|PPC476, {RB}},
6235 {"slbfee.", XRC(31,979,1), XRA_MASK, POWER6, 0, {RT, RB}},
6237 {"stbcix", X(31,981), X_MASK, POWER6, 0, {RS, RA0, RB}},
6239 {"icbi", X(31,982), XRT_MASK, PPC, 0, {RA0, RB}},
6241 {"stfiwx", X(31,983), X_MASK, PPC, PPCEFS, {FRS, RA0, RB}},
6246 {"icbiep", XRT(31,991,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}},
6248 {"stvswxl", X(31,997), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
6250 {"icread", X(31,998), XRT_MASK, PPC403|PPC440|PPC476|TITAN, 0, {RA0, RB}},
6255 {"divdo", XO(31,489,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
6256 {"divdo.", XO(31,489,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
6258 {"divwo", XO(31,491,1,0), XO_MASK, PPC, 0, {RT, RA, RB}},
6259 {"divwo.", XO(31,491,1,1), XO_MASK, PPC, 0, {RT, RA, RB}},
6261 {"stxvb16x", X(31,1004), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
6265 {"tlbli", X(31,1010), XRTRA_MASK, PPC, TITAN, {RB}},
6267 {"stdcix", X(31,1013), X_MASK, POWER6, 0, {RS, RA0, RB}},
6269 {"dcbz", X(31,1014), XRT_MASK, PPC, 0, {RA0, RB}},
6270 {"dclz", X(31,1014), XRT_MASK, PPC, 0, {RA0, RB}},
6272 {"dcbzep", XRT(31,1023,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}},
6274 {"dcbzl", XOPL(31,1014,1), XRT_MASK, POWER4|E500MC, PPC476, {RA0, RB}},
6280 {"dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}},
6281 {"dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}},
6641 {"xsiexpdp", X(60,918), XX1_MASK, PPCVSX3, PPCVLE, {XT6, RA, RB}},
7152 {"e_cmph", X(31,14), X_MASK, PPCVLE, 0, {CRD, RA, RB}},
7153 {"e_cmphl", X(31,46), X_MASK, PPCVLE, 0, {CRD, RA, RB}},
7166 {"e_rlw", EX(31,560), EX_MASK, PPCVLE, 0, {RA, RS, RB}},
7167 {"e_rlw.", EX(31,561), EX_MASK, PPCVLE, 0, {RA, RS, RB}},