Lines Matching refs:mpic
2 * arch/powerpc/kernel/mpic.c
41 #include <asm/mpic.h>
44 #include "mpic.h"
53 .name = "mpic",
54 .dev_name = "mpic",
58 static struct mpic *mpics;
59 static struct mpic *mpic_primary;
152 #define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name]
160 static inline unsigned int mpic_processor_id(struct mpic *mpic)
164 if (!(mpic->flags & MPIC_SECONDARY))
212 static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi)
214 enum mpic_reg_type type = mpic->reg_type;
218 if ((mpic->flags & MPIC_BROKEN_IPI) && type == mpic_access_mmio_le)
220 return _mpic_read(type, &mpic->gregs, offset);
223 static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value)
228 _mpic_write(mpic->reg_type, &mpic->gregs, offset, value);
231 static inline unsigned int mpic_tm_offset(struct mpic *mpic, unsigned int tm)
237 static inline u32 _mpic_tm_read(struct mpic *mpic, unsigned int tm)
239 unsigned int offset = mpic_tm_offset(mpic, tm) +
242 return _mpic_read(mpic->reg_type, &mpic->tmregs, offset);
245 static inline void _mpic_tm_write(struct mpic *mpic, unsigned int tm, u32 value)
247 unsigned int offset = mpic_tm_offset(mpic, tm) +
250 _mpic_write(mpic->reg_type, &mpic->tmregs, offset, value);
253 static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg)
255 unsigned int cpu = mpic_processor_id(mpic);
257 return _mpic_read(mpic->reg_type, &mpic->cpuregs[cpu], reg);
260 static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value)
262 unsigned int cpu = mpic_processor_id(mpic);
264 _mpic_write(mpic->reg_type, &mpic->cpuregs[cpu], reg, value);
267 static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigned int reg)
269 unsigned int isu = src_no >> mpic->isu_shift;
270 unsigned int idx = src_no & mpic->isu_mask;
273 val = _mpic_read(mpic->reg_type, &mpic->isus[isu],
278 mpic->isu_reg0_shadow[src_no];
283 static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no,
286 unsigned int isu = src_no >> mpic->isu_shift;
287 unsigned int idx = src_no & mpic->isu_mask;
289 _mpic_write(mpic->reg_type, &mpic->isus[isu],
294 mpic->isu_reg0_shadow[src_no] =
299 #define mpic_read(b,r) _mpic_read(mpic->reg_type,&(b),(r))
300 #define mpic_write(b,r,v) _mpic_write(mpic->reg_type,&(b),(r),(v))
301 #define mpic_ipi_read(i) _mpic_ipi_read(mpic,(i))
302 #define mpic_ipi_write(i,v) _mpic_ipi_write(mpic,(i),(v))
303 #define mpic_tm_read(i) _mpic_tm_read(mpic,(i))
304 #define mpic_tm_write(i,v) _mpic_tm_write(mpic,(i),(v))
305 #define mpic_cpu_read(i) _mpic_cpu_read(mpic,(i))
306 #define mpic_cpu_write(i,v) _mpic_cpu_write(mpic,(i),(v))
307 #define mpic_irq_read(s,r) _mpic_irq_read(mpic,(s),(r))
308 #define mpic_irq_write(s,r,v) _mpic_irq_write(mpic,(s),(r),(v))
316 static void _mpic_map_mmio(struct mpic *mpic, phys_addr_t phys_addr,
325 static void _mpic_map_dcr(struct mpic *mpic, struct mpic_reg_bank *rb,
328 phys_addr_t phys_addr = dcr_resource_start(mpic->node, 0);
329 rb->dhost = dcr_map(mpic->node, phys_addr + offset, size);
333 static inline void mpic_map(struct mpic *mpic,
337 if (mpic->flags & MPIC_USES_DCR)
338 _mpic_map_dcr(mpic, rb, offset, size);
340 _mpic_map_mmio(mpic, phys_addr, rb, offset, size);
351 static void __init mpic_test_broken_ipi(struct mpic *mpic)
355 mpic_write(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0), MPIC_VECPRI_MASK);
356 r = mpic_read(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0));
359 printk(KERN_INFO "mpic: Detected reversed IPI registers\n");
360 mpic->flags |= MPIC_BROKEN_IPI;
369 static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
371 if (source >= 128 || !mpic->fixups)
373 return mpic->fixups[source].base != NULL;
377 static inline void mpic_ht_end_irq(struct mpic *mpic, unsigned int source)
379 struct mpic_irq_fixup *fixup = &mpic->fixups[source];
386 raw_spin_lock(&mpic->fixup_lock);
389 raw_spin_unlock(&mpic->fixup_lock);
393 static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source,
396 struct mpic_irq_fixup *fixup = &mpic->fixups[source];
405 raw_spin_lock_irqsave(&mpic->fixup_lock, flags);
413 raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags);
418 mpic->save_data[source].fixup_data = tmp | 1;
422 static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source)
424 struct mpic_irq_fixup *fixup = &mpic->fixups[source];
434 raw_spin_lock_irqsave(&mpic->fixup_lock, flags);
439 raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags);
444 mpic->save_data[source].fixup_data = tmp & ~1;
449 static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
477 printk(KERN_DEBUG "mpic: - HT:%02x.%x %s MSI mapping found @ 0x%llx\n",
485 static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
492 static void __init mpic_scan_ht_pic(struct mpic *mpic, u8 __iomem *devbase,
516 printk(KERN_INFO "mpic: - HT:%02x.%x [0x%02x] vendor %04x device %04x"
528 mpic->fixups[irq].index = i;
529 mpic->fixups[irq].base = base;
532 mpic->fixups[irq].applebase = devbase + 0x60;
534 mpic->fixups[irq].applebase = NULL;
536 mpic->fixups[irq].data = readl(base + 4) | 0x80000000;
541 static void __init mpic_scan_ht_pics(struct mpic *mpic)
546 printk(KERN_INFO "mpic: Setting up HT PICs workarounds for U3/U4\n");
549 mpic->fixups = kcalloc(128, sizeof(*mpic->fixups), GFP_KERNEL);
550 BUG_ON(mpic->fixups == NULL);
553 raw_spin_lock_init(&mpic->fixup_lock);
581 mpic_scan_ht_pic(mpic, devbase, devfn, l);
582 mpic_scan_ht_msi(mpic, devbase, devfn);
593 static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
598 static void __init mpic_scan_ht_pics(struct mpic *mpic)
604 /* Find an mpic associated with a given linux interrupt */
605 static struct mpic *mpic_find(unsigned int irq)
614 static unsigned int mpic_is_ipi(struct mpic *mpic, unsigned int src)
616 return (src >= mpic->ipi_vecs[0] && src <= mpic->ipi_vecs[3]);
620 static unsigned int mpic_is_tm(struct mpic *mpic, unsigned int src)
622 return (src >= mpic->timer_vecs[0] && src <= mpic->timer_vecs[7]);
637 /* Get the mpic structure from the IPI number */
638 static inline struct mpic * mpic_from_ipi(struct irq_data *d)
644 /* Get the mpic structure from the irq number */
645 static inline struct mpic * mpic_from_irq(unsigned int irq)
650 /* Get the mpic structure from the irq data */
651 static inline struct mpic * mpic_from_irq_data(struct irq_data *d)
657 static inline void mpic_eoi(struct mpic *mpic)
670 struct mpic *mpic = mpic_from_irq_data(d);
673 DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, d->irq, src);
691 struct mpic *mpic = mpic_from_irq_data(d);
694 DBG("%s: disable_irq: %d (src %d)\n", mpic->name, d->irq, src);
712 struct mpic *mpic = mpic_from_irq_data(d);
715 DBG("%s: end_irq: %d\n", mpic->name, d->irq);
722 mpic_eoi(mpic);
729 struct mpic *mpic = mpic_from_irq_data(d);
735 mpic_ht_end_irq(mpic, src);
740 struct mpic *mpic = mpic_from_irq_data(d);
744 mpic_startup_ht_interrupt(mpic, src, irqd_is_level_type(d));
751 struct mpic *mpic = mpic_from_irq_data(d);
754 mpic_shutdown_ht_interrupt(mpic, src);
760 struct mpic *mpic = mpic_from_irq_data(d);
764 DBG("%s: end_irq: %d\n", mpic->name, d->irq);
772 mpic_ht_end_irq(mpic, src);
773 mpic_eoi(mpic);
781 struct mpic *mpic = mpic_from_ipi(d);
782 unsigned int src = virq_to_hw(d->irq) - mpic->ipi_vecs[0];
784 DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, d->irq, src);
795 struct mpic *mpic = mpic_from_ipi(d);
802 mpic_eoi(mpic);
809 struct mpic *mpic = mpic_from_irq_data(d);
810 unsigned int src = virq_to_hw(d->irq) - mpic->timer_vecs[0];
812 DBG("%s: enable_tm: %d (tm %d)\n", mpic->name, d->irq, src);
819 struct mpic *mpic = mpic_from_irq_data(d);
820 unsigned int src = virq_to_hw(d->irq) - mpic->timer_vecs[0];
829 struct mpic *mpic = mpic_from_irq_data(d);
832 if (mpic->flags & MPIC_SINGLE_DEST_CPU) {
848 static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type)
871 struct mpic *mpic = mpic_from_irq_data(d);
875 DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n",
876 mpic, d->irq, src, flow_type);
878 if (src >= mpic->num_sources)
907 WARN_ONCE(1, "mpic: unknown IRQ type %d\n", vold);
914 if (mpic_is_ht_interrupt(mpic, src))
918 vecpri = mpic_type_to_vecpri(mpic, flow_type);
931 struct mpic *mpic = mpic_from_irq(virq);
935 DBG("mpic: set_vector(mpic:@%p,virq:%d,src:%d,vector:0x%x)\n",
936 mpic, virq, src, vector);
938 if (src >= mpic->num_sources)
949 struct mpic *mpic = mpic_from_irq(virq);
952 DBG("mpic: set_destination(mpic:@%p,virq:%d,src:%d,cpuid:0x%x)\n",
953 mpic, virq, src, cpuid);
955 if (src >= mpic->num_sources)
997 /* Exact match, unless mpic node is NULL */
1005 struct mpic *mpic = h->host_data;
1008 DBG("mpic: map virq %d, hwirq 0x%lx\n", virq, hw);
1010 if (hw == mpic->spurious_vec)
1012 if (mpic->protected && test_bit(hw, mpic->protected)) {
1013 pr_warn("mpic: Mapping of source 0x%x failed, source protected by firmware !\n",
1019 else if (hw >= mpic->ipi_vecs[0]) {
1020 WARN_ON(mpic->flags & MPIC_SECONDARY);
1022 DBG("mpic: mapping as IPI\n");
1023 irq_set_chip_data(virq, mpic);
1024 irq_set_chip_and_handler(virq, &mpic->hc_ipi,
1030 if (hw >= mpic->timer_vecs[0] && hw <= mpic->timer_vecs[7]) {
1031 WARN_ON(mpic->flags & MPIC_SECONDARY);
1033 DBG("mpic: mapping as timer\n");
1034 irq_set_chip_data(virq, mpic);
1035 irq_set_chip_and_handler(virq, &mpic->hc_tm,
1040 if (mpic_map_error_int(mpic, virq, hw))
1043 if (hw >= mpic->num_sources) {
1044 pr_warn("mpic: Mapping of source 0x%x failed, source out of range !\n",
1049 mpic_msi_reserve_hwirq(mpic, hw);
1052 chip = &mpic->hc_irq;
1056 if (mpic_is_ht_interrupt(mpic, hw))
1057 chip = &mpic->hc_ht_irq;
1060 DBG("mpic: mapping to irq chip @%p\n", chip);
1062 irq_set_chip_data(virq, mpic);
1072 if (!mpic_is_ipi(mpic, hw) && (mpic->flags & MPIC_NO_RESET)) {
1076 cpu = mpic_processor_id(mpic);
1092 struct mpic *mpic = h->host_data;
1101 if (intsize >= 4 && (mpic->flags & MPIC_FSL)) {
1107 * See Documentation/devicetree/bindings/powerpc/fsl/mpic.txt
1113 if (!(mpic->flags & MPIC_FSL_HAS_EIMR))
1116 if (intspec[3] >= ARRAY_SIZE(mpic->err_int_vecs))
1119 *out_hwirq = mpic->err_int_vecs[intspec[3]];
1123 if (intspec[0] >= ARRAY_SIZE(mpic->ipi_vecs))
1126 *out_hwirq = mpic->ipi_vecs[intspec[0]];
1129 if (intspec[0] >= ARRAY_SIZE(mpic->timer_vecs))
1132 *out_hwirq = mpic->timer_vecs[intspec[0]];
1160 DBG("mpic: xlate (%d cells: 0x%08x 0x%08x) to line 0x%lx sense 0x%x\n",
1170 struct mpic *mpic = irq_desc_get_handler_data(desc);
1173 BUG_ON(!(mpic->flags & MPIC_SECONDARY));
1175 virq = mpic_get_one_irq(mpic);
1188 static u32 fsl_mpic_get_version(struct mpic *mpic)
1192 if (!(mpic->flags & MPIC_FSL))
1195 brr1 = _mpic_read(mpic->reg_type, &mpic->thiscpuregs,
1207 struct mpic *mpic = mpic_primary;
1209 if (mpic)
1210 return fsl_mpic_get_version(mpic);
1215 struct mpic * __init mpic_alloc(struct device_node *node,
1223 struct mpic *mpic;
1269 if (of_device_is_compatible(node, "fsl,mpic")) {
1275 mpic = kzalloc(sizeof(struct mpic), GFP_KERNEL);
1276 if (mpic == NULL)
1279 mpic->name = name;
1280 mpic->node = node;
1281 mpic->paddr = phys_addr;
1282 mpic->flags = flags;
1284 mpic->hc_irq = mpic_irq_chip;
1285 mpic->hc_irq.name = name;
1286 if (!(mpic->flags & MPIC_SECONDARY))
1287 mpic->hc_irq.irq_set_affinity = mpic_set_affinity;
1289 mpic->hc_ht_irq = mpic_irq_ht_chip;
1290 mpic->hc_ht_irq.name = name;
1291 if (!(mpic->flags & MPIC_SECONDARY))
1292 mpic->hc_ht_irq.irq_set_affinity = mpic_set_affinity;
1296 mpic->hc_ipi = mpic_ipi_chip;
1297 mpic->hc_ipi.name = name;
1300 mpic->hc_tm = mpic_tm_chip;
1301 mpic->hc_tm.name = name;
1303 mpic->num_sources = 0; /* so far */
1305 if (mpic->flags & MPIC_LARGE_VECTORS)
1310 mpic->timer_vecs[0] = intvec_top - 12;
1311 mpic->timer_vecs[1] = intvec_top - 11;
1312 mpic->timer_vecs[2] = intvec_top - 10;
1313 mpic->timer_vecs[3] = intvec_top - 9;
1314 mpic->timer_vecs[4] = intvec_top - 8;
1315 mpic->timer_vecs[5] = intvec_top - 7;
1316 mpic->timer_vecs[6] = intvec_top - 6;
1317 mpic->timer_vecs[7] = intvec_top - 5;
1318 mpic->ipi_vecs[0] = intvec_top - 4;
1319 mpic->ipi_vecs[1] = intvec_top - 3;
1320 mpic->ipi_vecs[2] = intvec_top - 2;
1321 mpic->ipi_vecs[3] = intvec_top - 1;
1322 mpic->spurious_vec = intvec_top;
1325 psrc = of_get_property(mpic->node, "protected-sources", &psize);
1328 mpic->protected = bitmap_zalloc(intvec_top + 1, GFP_KERNEL);
1329 BUG_ON(mpic->protected == NULL);
1333 __set_bit(psrc[i], mpic->protected);
1338 mpic->hw_set = mpic_infos[MPIC_GET_REGSET(mpic->flags)];
1342 if (mpic->flags & MPIC_BIG_ENDIAN)
1343 mpic->reg_type = mpic_access_mmio_be;
1345 mpic->reg_type = mpic_access_mmio_le;
1352 if (mpic->flags & MPIC_USES_DCR)
1353 mpic->reg_type = mpic_access_dcr;
1355 BUG_ON(mpic->flags & MPIC_USES_DCR);
1359 mpic_map(mpic, mpic->paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000);
1360 mpic_map(mpic, mpic->paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000);
1362 if (mpic->flags & MPIC_FSL) {
1370 mpic_map(mpic, mpic->paddr, &mpic->thiscpuregs,
1373 fsl_version = fsl_mpic_get_version(mpic);
1389 ret = mpic_setup_error_int(mpic, intvec_top - 13);
1405 * an "fsl,mpic" compatible at all. This will be the case
1417 if (!(mpic->flags & MPIC_NO_RESET)) {
1418 printk(KERN_DEBUG "mpic: Resetting\n");
1419 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1420 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1422 while( mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1428 if (mpic->flags & MPIC_ENABLE_COREINT)
1429 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1430 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1433 if (mpic->flags & MPIC_ENABLE_MCK)
1434 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1435 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1448 mpic_map(mpic, mpic->paddr, &mpic->cpuregs[cpu],
1457 greg_feature = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0));
1469 of_property_read_u32(mpic->node, "last-interrupt-source", &last_irq);
1476 mpic->num_sources = isu_size;
1477 mpic_map(mpic, mpic->paddr, &mpic->isus[0],
1482 mpic->isu_size = isu_size;
1483 mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1);
1484 mpic->isu_mask = (1 << mpic->isu_shift) - 1;
1486 mpic->irqhost = irq_domain_add_linear(mpic->node,
1488 &mpic_host_ops, mpic);
1494 if (mpic->irqhost == NULL)
1512 printk(KERN_INFO "mpic: Setting up MPIC \"%s\" version %s at %llx,"
1514 name, vers, (unsigned long long)mpic->paddr, num_possible_cpus());
1515 printk(KERN_INFO "mpic: ISU size: %d, shift: %d, mask: %x\n",
1516 mpic->isu_size, mpic->isu_shift, mpic->isu_mask);
1518 mpic->next = mpics;
1519 mpics = mpic;
1521 if (!(mpic->flags & MPIC_SECONDARY)) {
1522 mpic_primary = mpic;
1523 irq_set_default_host(mpic->irqhost);
1526 return mpic;
1533 void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
1536 unsigned int isu_first = isu_num * mpic->isu_size;
1540 mpic_map(mpic,
1541 paddr, &mpic->isus[isu_num], 0,
1542 MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
1544 if ((isu_first + mpic->isu_size) > mpic->num_sources)
1545 mpic->num_sources = isu_first + mpic->isu_size;
1548 void __init mpic_init(struct mpic *mpic)
1553 BUG_ON(mpic->num_sources == 0);
1555 printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources);
1560 if (mpic->flags & MPIC_FSL) {
1561 u32 version = fsl_mpic_get_version(mpic);
1575 unsigned int offset = mpic_tm_offset(mpic, i);
1577 mpic_write(mpic->tmregs,
1580 mpic_write(mpic->tmregs,
1584 (mpic->timer_vecs[0] + i));
1588 mpic_test_broken_ipi(mpic);
1593 (mpic->ipi_vecs[0] + i));
1596 /* Do the HT PIC fixups on U3 broken mpic */
1597 DBG("MPIC flags: %x\n", mpic->flags);
1598 if ((mpic->flags & MPIC_U3_HT_IRQS) && !(mpic->flags & MPIC_SECONDARY)) {
1599 mpic_scan_ht_pics(mpic);
1600 mpic_u3msi_init(mpic);
1603 mpic_pasemi_msi_init(mpic);
1605 cpu = mpic_processor_id(mpic);
1607 if (!(mpic->flags & MPIC_NO_RESET)) {
1608 for (i = 0; i < mpic->num_sources; i++) {
1614 if (mpic->protected && test_bit(i, mpic->protected))
1623 mpic_write(mpic->gregs, MPIC_INFO(GREG_SPURIOUS), mpic->spurious_vec);
1626 if (!(mpic->flags & MPIC_NO_PTHROU_DIS))
1627 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1628 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1631 if (mpic->flags & MPIC_NO_BIAS)
1632 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1633 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1640 /* allocate memory to save mpic state */
1641 mpic->save_data = kmalloc_array(mpic->num_sources,
1642 sizeof(*mpic->save_data),
1644 BUG_ON(mpic->save_data == NULL);
1648 if (mpic->flags & MPIC_SECONDARY) {
1649 int virq = irq_of_parse_and_map(mpic->node, 0);
1652 mpic->node, virq);
1653 irq_set_handler_data(virq, mpic);
1658 /* FSL mpic error interrupt initialization */
1659 if (mpic->flags & MPIC_FSL_HAS_EIMR)
1660 mpic_err_int_init(mpic, MPIC_FSL_ERR_INT);
1665 struct mpic *mpic = mpic_find(irq);
1670 if (!mpic)
1674 if (mpic_is_ipi(mpic, src)) {
1675 reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) &
1677 mpic_ipi_write(src - mpic->ipi_vecs[0],
1679 } else if (mpic_is_tm(mpic, src)) {
1680 reg = mpic_tm_read(src - mpic->timer_vecs[0]) &
1682 mpic_tm_write(src - mpic->timer_vecs[0],
1696 struct mpic *mpic = mpic_primary;
1701 BUG_ON(mpic == NULL);
1703 DBG("%s: setup_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
1707 /* let the mpic know we want intrs. default affinity is 0xffffffff
1712 if (distribute_irqs && !(mpic->flags & MPIC_SINGLE_DEST_CPU)) {
1713 for (i = 0; i < mpic->num_sources ; i++)
1727 struct mpic *mpic = mpic_primary;
1734 struct mpic *mpic = mpic_primary;
1742 struct mpic *mpic = mpic_primary;
1747 BUG_ON(mpic == NULL);
1749 DBG("%s: teardown_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
1752 /* let the mpic know we don't want intrs. */
1753 for (i = 0; i < mpic->num_sources ; i++)
1762 mpic_eoi(mpic);
1768 static unsigned int _mpic_get_one_irq(struct mpic *mpic, int reg)
1774 DBG("%s: get_one_irq(reg 0x%x): %d\n", mpic->name, reg, src);
1776 if (unlikely(src == mpic->spurious_vec)) {
1777 if (mpic->flags & MPIC_SPV_EOI)
1778 mpic_eoi(mpic);
1781 if (unlikely(mpic->protected && test_bit(src, mpic->protected))) {
1783 mpic->name, (int)src);
1784 mpic_eoi(mpic);
1788 return irq_linear_revmap(mpic->irqhost, src);
1791 unsigned int mpic_get_one_irq(struct mpic *mpic)
1793 return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_INTACK));
1798 struct mpic *mpic = mpic_primary;
1800 BUG_ON(mpic == NULL);
1802 return mpic_get_one_irq(mpic);
1808 struct mpic *mpic = mpic_primary;
1811 BUG_ON(mpic == NULL);
1815 if (unlikely(src == mpic->spurious_vec)) {
1816 if (mpic->flags & MPIC_SPV_EOI)
1817 mpic_eoi(mpic);
1820 if (unlikely(mpic->protected && test_bit(src, mpic->protected))) {
1822 mpic->name, (int)src);
1826 return irq_linear_revmap(mpic->irqhost, src);
1834 struct mpic *mpic = mpic_primary;
1836 BUG_ON(mpic == NULL);
1838 return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_MCACK));
1844 struct mpic *mpic = mpic_primary;
1846 BUG_ON(mpic == NULL);
1848 printk(KERN_INFO "mpic: requesting IPIs...\n");
1851 unsigned int vipi = irq_create_mapping(mpic->irqhost,
1852 mpic->ipi_vecs[0] + i);
1863 struct mpic *mpic = mpic_primary;
1866 BUG_ON(mpic == NULL);
1876 DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, msg);
1906 struct mpic *mpic = mpic_primary;
1912 pir = mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
1914 mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir);
1915 mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
1919 mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir);
1920 mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
1924 if (mpic->flags & MPIC_FSL) {
1926 _mpic_write(mpic->reg_type, &mpic->cpuregs[cpuid],
1934 static void mpic_suspend_one(struct mpic *mpic)
1938 for (i = 0; i < mpic->num_sources; i++) {
1939 mpic->save_data[i].vecprio =
1941 mpic->save_data[i].dest =
1948 struct mpic *mpic = mpics;
1950 while (mpic) {
1951 mpic_suspend_one(mpic);
1952 mpic = mpic->next;
1958 static void mpic_resume_one(struct mpic *mpic)
1962 for (i = 0; i < mpic->num_sources; i++) {
1964 mpic->save_data[i].vecprio);
1966 mpic->save_data[i].dest);
1969 if (mpic->fixups) {
1970 struct mpic_irq_fixup *fixup = &mpic->fixups[i];
1974 if ((mpic->save_data[i].fixup_data & 1) == 0)
1980 writel(mpic->save_data[i].fixup_data & ~1,
1990 struct mpic *mpic = mpics;
1992 while (mpic) {
1993 mpic_resume_one(mpic);
1994 mpic = mpic->next;
2011 pr_err("mpic: Failed to register subsystem!\n");