Lines Matching defs:ipic
3 * arch/powerpc/sysdev/ipic.c
25 #include <asm/ipic.h>
27 #include "ipic.h"
29 static struct ipic * primary_ipic;
516 static inline struct ipic * ipic_from_irq(unsigned int virq)
523 struct ipic *ipic = ipic_from_irq(d->irq);
530 temp = ipic_read(ipic->regs, ipic_info[src].mask);
532 ipic_write(ipic->regs, ipic_info[src].mask, temp);
539 struct ipic *ipic = ipic_from_irq(d->irq);
546 temp = ipic_read(ipic->regs, ipic_info[src].mask);
548 ipic_write(ipic->regs, ipic_info[src].mask, temp);
559 struct ipic *ipic = ipic_from_irq(d->irq);
567 ipic_write(ipic->regs, ipic_info[src].ack, temp);
578 struct ipic *ipic = ipic_from_irq(d->irq);
585 temp = ipic_read(ipic->regs, ipic_info[src].mask);
587 ipic_write(ipic->regs, ipic_info[src].mask, temp);
590 ipic_write(ipic->regs, ipic_info[src].ack, temp);
601 struct ipic *ipic = ipic_from_irq(d->irq);
608 /* ipic supports only low assertion and high-to-low change senses
611 printk(KERN_ERR "ipic: sense type 0x%x not supported\n",
615 /* ipic supports only edge mode on external interrupts */
617 printk(KERN_ERR "ipic: edge sense not supported on internal "
632 /* only EXT IRQ senses are programmable on ipic
643 vold = ipic_read(ipic->regs, IPIC_SECNR);
650 ipic_write(ipic->regs, IPIC_SECNR, vnew);
675 /* Exact match, unless ipic node is NULL */
683 struct ipic *ipic = h->host_data;
685 irq_set_chip_data(virq, ipic);
700 struct ipic * __init ipic_init(struct device_node *node, unsigned int flags)
702 struct ipic *ipic;
710 ipic = kzalloc(sizeof(*ipic), GFP_KERNEL);
711 if (ipic == NULL)
714 ipic->irqhost = irq_domain_add_linear(node, NR_IPIC_INTS,
715 &ipic_host_ops, ipic);
716 if (ipic->irqhost == NULL) {
717 kfree(ipic);
721 ipic->regs = ioremap(res.start, resource_size(&res));
724 ipic_write(ipic->regs, IPIC_SICNR, 0x0);
741 ipic_write(ipic->regs, IPIC_SICFR, temp);
747 ipic_write(ipic->regs, IPIC_SERCR, temp);
750 temp = ipic_read(ipic->regs, IPIC_SEMSR);
757 ipic_write(ipic->regs, IPIC_SEMSR, temp);
759 primary_ipic = ipic;
762 ipic_write(ipic->regs, IPIC_SIMSR_H, 0);
763 ipic_write(ipic->regs, IPIC_SIMSR_L, 0);
768 return ipic;
822 struct ipic *ipic = primary_ipic;
824 ipic_saved_state.sicfr = ipic_read(ipic->regs, IPIC_SICFR);
825 ipic_saved_state.siprr[0] = ipic_read(ipic->regs, IPIC_SIPRR_A);
826 ipic_saved_state.siprr[1] = ipic_read(ipic->regs, IPIC_SIPRR_D);
827 ipic_saved_state.simsr[0] = ipic_read(ipic->regs, IPIC_SIMSR_H);
828 ipic_saved_state.simsr[1] = ipic_read(ipic->regs, IPIC_SIMSR_L);
829 ipic_saved_state.sicnr = ipic_read(ipic->regs, IPIC_SICNR);
830 ipic_saved_state.smprr[0] = ipic_read(ipic->regs, IPIC_SMPRR_A);
831 ipic_saved_state.smprr[1] = ipic_read(ipic->regs, IPIC_SMPRR_B);
832 ipic_saved_state.semsr = ipic_read(ipic->regs, IPIC_SEMSR);
833 ipic_saved_state.secnr = ipic_read(ipic->regs, IPIC_SECNR);
834 ipic_saved_state.sermr = ipic_read(ipic->regs, IPIC_SERMR);
835 ipic_saved_state.sercr = ipic_read(ipic->regs, IPIC_SERCR);
842 ipic_write(ipic->regs, IPIC_SIMSR_H, 0);
843 ipic_write(ipic->regs, IPIC_SIMSR_L, 0);
844 ipic_write(ipic->regs, IPIC_SEMSR, 0);
845 ipic_write(ipic->regs, IPIC_SERMR, 0);
853 struct ipic *ipic = primary_ipic;
855 ipic_write(ipic->regs, IPIC_SICFR, ipic_saved_state.sicfr);
856 ipic_write(ipic->regs, IPIC_SIPRR_A, ipic_saved_state.siprr[0]);
857 ipic_write(ipic->regs, IPIC_SIPRR_D, ipic_saved_state.siprr[1]);
858 ipic_write(ipic->regs, IPIC_SIMSR_H, ipic_saved_state.simsr[0]);
859 ipic_write(ipic->regs, IPIC_SIMSR_L, ipic_saved_state.simsr[1]);
860 ipic_write(ipic->regs, IPIC_SICNR, ipic_saved_state.sicnr);
861 ipic_write(ipic->regs, IPIC_SMPRR_A, ipic_saved_state.smprr[0]);
862 ipic_write(ipic->regs, IPIC_SMPRR_B, ipic_saved_state.smprr[1]);
863 ipic_write(ipic->regs, IPIC_SEMSR, ipic_saved_state.semsr);
864 ipic_write(ipic->regs, IPIC_SECNR, ipic_saved_state.secnr);
865 ipic_write(ipic->regs, IPIC_SERMR, ipic_saved_state.sermr);
866 ipic_write(ipic->regs, IPIC_SERCR, ipic_saved_state.sercr);
883 printk(KERN_DEBUG "Registering ipic system core operations\n");