Lines Matching refs:hose
68 static int fsl_pcie_check_link(struct pci_controller *hose)
72 if (hose->indirect_type & PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK) {
73 if (hose->ops->read == fsl_indirect_read_config)
74 __indirect_read_config(hose, hose->first_busno, 0,
77 early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val);
81 struct ccsr_pci __iomem *pci = hose->private_data;
95 struct pci_controller *hose = pci_bus_to_host(bus);
97 if (fsl_pcie_check_link(hose))
98 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
100 hose->indirect_type &= ~PPC_INDIRECT_TYPE_NO_PCIE_LINK;
118 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
121 hose->dma_window_base_cur + hose->dma_window_size - 1;
124 static void setup_swiotlb_ops(struct pci_controller *hose)
127 hose->controller_ops.dma_dev_setup = pci_dma_dev_setup_swiotlb;
130 static inline void setup_swiotlb_ops(struct pci_controller *hose) {}
199 static void setup_pci_atmu(struct pci_controller *hose)
201 struct ccsr_pci __iomem *pci = hose->private_data;
217 * hose->dma_window_size still get set.
221 if (of_device_is_compatible(hose->dn, "fsl,bsc9132-pcie")) {
234 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
253 if (!(hose->mem_resources[i].flags & IORESOURCE_MEM))
256 paddr_lo = min(paddr_lo, (u64)hose->mem_resources[i].start);
257 paddr_hi = max(paddr_hi, (u64)hose->mem_resources[i].end);
260 offset = hose->mem_offset[i];
261 n = setup_one_atmu(pci, j, &hose->mem_resources[i], offset);
265 hose->mem_resources[i].flags |= IORESOURCE_DISABLED;
271 if (hose->io_resource.flags & IORESOURCE_IO) {
277 (u64)hose->io_resource.start,
278 (u64)resource_size(&hose->io_resource),
279 (u64)hose->io_base_phys);
280 out_be32(&pci->pow[j].potar, (hose->io_resource.start >> 12));
282 out_be32(&pci->pow[j].powbar, (hose->io_base_phys >> 12));
285 | (ilog2(hose->io_resource.end
286 - hose->io_resource.start + 1) - 1));
295 pr_err("%pOF: No outbound window space\n", hose->dn);
300 pr_err("%pOF: No space for inbound window\n", hose->dn);
305 early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, 0xffffffff);
306 early_read_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, &pcicsrbar_sz);
314 early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, pcicsrbar);
318 pr_info("%pOF: PCICSRBAR @ 0x%x\n", hose->dn, pcicsrbar);
336 reg = of_get_property(hose->dn, "msi-address-64", &len);
341 pr_info("%pOF: extending DDR ATMU to cover MSIIR", hose->dn);
346 "unsupported\n", hose->dn, address);
354 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
360 "greater than memory size\n", hose->dn);
373 hose->dma_window_base_cur = 0x00000000;
374 hose->dma_window_size = (resource_size_t)sz;
407 pr_info("%pOF: Setup 64-bit PCI DMA window\n", hose->dn);
440 hose->dma_window_base_cur = 0x00000000;
441 hose->dma_window_size = (resource_size_t)paddr;
444 if (hose->dma_window_size < mem) {
450 hose->dn);
457 hose->dn);
459 pr_info("%pOF: DMA window size is 0x%llx\n", hose->dn,
460 (u64)hose->dma_window_size);
464 static void setup_pci_cmd(struct pci_controller *hose)
469 early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd);
472 early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd);
474 cap_x = early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX);
479 early_write_config_word(hose, 0, 0, pci_x_cmd, cmd);
481 early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
487 struct pci_controller *hose = pci_bus_to_host(bus);
499 is_pcie = early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP);
500 no_link = !!(hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK);
502 if (bus->parent == hose->bus && (is_pcie || no_link)) {
510 par = &hose->io_resource;
512 par = &hose->mem_resources[i-1];
525 struct pci_controller *hose;
557 hose = pcibios_alloc_controller(dev);
558 if (!hose)
562 hose->parent = &pdev->dev;
563 hose->first_busno = bus_range ? bus_range[0] : 0x0;
564 hose->last_busno = bus_range ? bus_range[1] : 0xff;
569 pci = hose->private_data = ioremap(rsrc.start, resource_size(&rsrc));
570 if (!hose->private_data)
573 setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
577 hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK;
579 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
581 hose->ops = &fsl_indirect_pcie_ops;
583 early_read_config_byte(hose, 0, 0, PCI_HEADER_TYPE, &hdr_type);
589 early_read_config_byte(hose, 0, 0, PCI_CLASS_PROG, &progif);
595 setup_pci_cmd(hose);
598 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
599 hose->indirect_type |= PPC_INDIRECT_TYPE_EXT_REG |
601 if (fsl_pcie_check_link(hose))
602 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
605 early_read_config_dword(hose, 0, 0, PCIE_FSL_CSR_CLASSCODE, &class_code);
608 early_write_config_dword(hose, 0, 0, PCIE_FSL_CSR_CLASSCODE, class_code);
624 !early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX)) {
625 early_read_config_word(hose, 0, 0,
628 early_write_config_word(hose, 0, 0,
635 (unsigned long long)rsrc.start, hose->first_busno,
636 hose->last_busno);
639 hose, hose->cfg_addr, hose->cfg_data);
643 pci_process_bridge_OF_ranges(hose, dev, is_primary);
646 setup_pci_atmu(hose);
649 setup_swiotlb_ops(hose);
654 iounmap(hose->private_data);
656 if (((unsigned long)hose->cfg_data & PAGE_MASK) !=
657 ((unsigned long)hose->cfg_addr & PAGE_MASK))
658 iounmap(hose->cfg_data);
659 iounmap(hose->cfg_addr);
660 pcibios_free_controller(hose);
694 struct pci_controller *hose = pci_bus_to_host(bus);
696 if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK)
703 if (bus->number == hose->first_busno ||
704 bus->primary == hose->first_busno) {
710 if (ppc_md.pci_exclude_device(hose, bus->number, devfn))
720 struct pci_controller *hose = pci_bus_to_host(bus);
721 struct mpc83xx_pcie_priv *pcie = hose->dn->data;
732 if (bus->number == hose->first_busno)
748 struct pci_controller *hose = pci_bus_to_host(bus);
751 if (offset == PCI_PRIMARY_BUS && bus->number == hose->first_busno)
763 static int __init mpc83xx_pcie_setup(struct pci_controller *hose,
789 WARN_ON(hose->dn->data);
790 hose->dn->data = pcie;
791 hose->ops = &mpc83xx_pcie_ops;
792 hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK;
797 if (fsl_pcie_check_link(hose))
798 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
813 struct pci_controller *hose;
866 hose = pcibios_alloc_controller(dev);
867 if (!hose)
870 hose->first_busno = bus_range ? bus_range[0] : 0;
871 hose->last_busno = bus_range ? bus_range[1] : 0xff;
874 ret = mpc83xx_pcie_setup(hose, &rsrc_reg);
878 setup_indirect_pci(hose, rsrc_cfg.start,
884 (unsigned long long)rsrc_reg.start, hose->first_busno,
885 hose->last_busno);
888 hose, hose->cfg_addr, hose->cfg_data);
892 pci_process_bridge_OF_ranges(hose, dev, primary);
896 pcibios_free_controller(hose);
901 u64 fsl_pci_immrbar_base(struct pci_controller *hose)
905 struct mpc83xx_pcie_priv *pcie = hose->dn->data;
929 pci_bus_read_config_dword(hose->bus,
1047 struct pci_controller *hose;
1051 list_for_each_entry(hose, &hose_list, list_node) {
1052 if (!(hose->indirect_type & PPC_INDIRECT_TYPE_EXT_REG))
1056 res = &hose->mem_resources[i];
1170 struct pci_controller *hose = dev_id;
1171 struct ccsr_pci __iomem *pci = hose->private_data;
1183 static int fsl_pci_pme_probe(struct pci_controller *hose)
1191 /* Get hose's pci_dev */
1192 dev = list_first_entry(&hose->bus->devices, typeof(*dev), bus_list);
1199 pme_irq = irq_of_parse_and_map(hose->dn, 0);
1206 res = devm_request_irq(hose->parent, pme_irq,
1209 "[PCI] PME", hose);
1217 pci = hose->private_data;
1235 static void send_pme_turnoff_message(struct pci_controller *hose)
1237 struct ccsr_pci __iomem *pci = hose->private_data;
1256 static void fsl_pci_syscore_do_suspend(struct pci_controller *hose)
1258 send_pme_turnoff_message(hose);
1263 struct pci_controller *hose, *tmp;
1265 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
1266 fsl_pci_syscore_do_suspend(hose);
1271 static void fsl_pci_syscore_do_resume(struct pci_controller *hose)
1273 struct ccsr_pci __iomem *pci = hose->private_data;
1291 setup_pci_atmu(hose);
1296 struct pci_controller *hose, *tmp;
1298 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
1299 fsl_pci_syscore_do_resume(hose);