Lines Matching refs:val
276 u64 lpcr, val;
282 val = 0ULL;
283 val = SET_FIELD(VAS_XLATE_MSR_HV, val, 1);
284 val = SET_FIELD(VAS_XLATE_MSR_SF, val, 1);
286 val = SET_FIELD(VAS_XLATE_MSR_DR, val, 1);
287 val = SET_FIELD(VAS_XLATE_MSR_PR, val, 1);
289 write_hvwc_reg(window, VREG(XLATE_MSR), val);
292 val = 0ULL;
300 val = SET_FIELD(VAS_XLATE_LPCR_PAGE_SIZE, val, 5);
301 val = SET_FIELD(VAS_XLATE_LPCR_ISL, val, lpcr & LPCR_ISL);
302 val = SET_FIELD(VAS_XLATE_LPCR_TC, val, lpcr & LPCR_TC);
303 val = SET_FIELD(VAS_XLATE_LPCR_SC, val, 0);
304 write_hvwc_reg(window, VREG(XLATE_LPCR), val);
313 val = 0ULL;
314 val = SET_FIELD(VAS_XLATE_MODE, val, radix_enabled() ? 3 : 2);
315 write_hvwc_reg(window, VREG(XLATE_CTL), val);
320 val = 0ULL;
321 val = SET_FIELD(VAS_AMR, val, mfspr(SPRN_AMR));
322 write_hvwc_reg(window, VREG(AMR), val);
324 val = 0ULL;
325 val = SET_FIELD(VAS_SEIDR, val, 0);
326 write_hvwc_reg(window, VREG(SEIDR), val);
364 u64 val;
369 val = 0ULL;
370 val = SET_FIELD(VAS_LPID, val, winctx->lpid);
371 write_hvwc_reg(window, VREG(LPID), val);
373 val = 0ULL;
374 val = SET_FIELD(VAS_PID_ID, val, winctx->pidr);
375 write_hvwc_reg(window, VREG(PID), val);
379 val = 0ULL;
380 val = SET_FIELD(VAS_FAULT_TX_WIN, val, winctx->fault_win_id);
381 write_hvwc_reg(window, VREG(FAULT_TX_WIN), val);
386 val = 0ULL;
387 val = SET_FIELD(VAS_HV_INTR_SRC_RA, val, winctx->irq_port);
388 write_hvwc_reg(window, VREG(HV_INTR_SRC_RA), val);
390 val = 0ULL;
391 val = SET_FIELD(VAS_PSWID_EA_HANDLE, val, winctx->pswid);
392 write_hvwc_reg(window, VREG(PSWID), val);
407 val = winctx->rx_fifo;
408 val = SET_FIELD(VAS_PAGE_MIGRATION_SELECT, val, 0);
409 write_hvwc_reg(window, VREG(LFIFO_BAR), val);
411 val = 0ULL;
412 val = SET_FIELD(VAS_LDATA_STAMP, val, winctx->data_stamp);
413 write_hvwc_reg(window, VREG(LDATA_STAMP_CTL), val);
415 val = 0ULL;
416 val = SET_FIELD(VAS_LDMA_TYPE, val, winctx->dma_type);
417 val = SET_FIELD(VAS_LDMA_FIFO_DISABLE, val, winctx->fifo_disable);
418 write_hvwc_reg(window, VREG(LDMA_CACHE_CTL), val);
424 val = 0ULL;
425 val = SET_FIELD(VAS_LRX_WCRED, val, winctx->wcreds_max);
426 write_hvwc_reg(window, VREG(LRX_WCRED), val);
428 val = 0ULL;
429 val = SET_FIELD(VAS_TX_WCRED, val, winctx->wcreds_max);
430 write_hvwc_reg(window, VREG(TX_WCRED), val);
437 val = 0ULL;
438 val = SET_FIELD(VAS_LFIFO_SIZE, val, ilog2(fifo_size));
439 write_hvwc_reg(window, VREG(LFIFO_SIZE), val);
451 val = 0ULL;
452 val = SET_FIELD(VAS_LRX_WIN_ID, val, winctx->rx_win_id);
453 write_hvwc_reg(window, VREG(LRFIFO_WIN_PTR), val);
457 val = 0ULL;
458 val = SET_FIELD(VAS_NOTIFY_DISABLE, val, winctx->notify_disable);
459 val = SET_FIELD(VAS_INTR_DISABLE, val, winctx->intr_disable);
460 val = SET_FIELD(VAS_NOTIFY_EARLY, val, winctx->notify_early);
461 val = SET_FIELD(VAS_NOTIFY_OSU_INTR, val, winctx->notify_os_intr_reg);
462 write_hvwc_reg(window, VREG(LNOTIFY_CTL), val);
464 val = 0ULL;
465 val = SET_FIELD(VAS_LNOTIFY_PID, val, winctx->lnotify_pid);
466 write_hvwc_reg(window, VREG(LNOTIFY_PID), val);
468 val = 0ULL;
469 val = SET_FIELD(VAS_LNOTIFY_LPID, val, winctx->lnotify_lpid);
470 write_hvwc_reg(window, VREG(LNOTIFY_LPID), val);
472 val = 0ULL;
473 val = SET_FIELD(VAS_LNOTIFY_TID, val, winctx->lnotify_tid);
474 write_hvwc_reg(window, VREG(LNOTIFY_TID), val);
476 val = 0ULL;
477 val = SET_FIELD(VAS_LNOTIFY_MIN_SCOPE, val, winctx->min_scope);
478 val = SET_FIELD(VAS_LNOTIFY_MAX_SCOPE, val, winctx->max_scope);
479 write_hvwc_reg(window, VREG(LNOTIFY_SCOPE), val);
488 val = 0ULL;
489 val = SET_FIELD(VAS_PUSH_TO_MEM, val, 1);
490 write_hvwc_reg(window, VREG(WIN_CTX_CACHING_CTL), val);
493 val = 0ULL;
494 val = SET_FIELD(VAS_WINCTL_REJ_NO_CREDIT, val, winctx->rej_no_credit);
495 val = SET_FIELD(VAS_WINCTL_PIN, val, winctx->pin_win);
496 val = SET_FIELD(VAS_WINCTL_TX_WCRED_MODE, val, winctx->tx_wcred_mode);
497 val = SET_FIELD(VAS_WINCTL_RX_WCRED_MODE, val, winctx->rx_wcred_mode);
498 val = SET_FIELD(VAS_WINCTL_TX_WORD_MODE, val, winctx->tx_word_mode);
499 val = SET_FIELD(VAS_WINCTL_RX_WORD_MODE, val, winctx->rx_word_mode);
500 val = SET_FIELD(VAS_WINCTL_FAULT_WIN, val, winctx->fault_win);
501 val = SET_FIELD(VAS_WINCTL_NX_WIN, val, winctx->nx_win);
502 val = SET_FIELD(VAS_WINCTL_OPEN, val, 1);
503 write_hvwc_reg(window, VREG(WINCTL), val);
1103 uint64_t val;
1121 val = SET_FIELD(RMA_LSMP_REPORT_ENABLE, 0ULL, 1);
1122 addr += val;
1157 u64 val;
1161 val = read_hvwc_reg(window, VREG(WINCTL));
1163 mode = GET_FIELD(VAS_WINCTL_TX_WCRED_MODE, val);
1165 mode = GET_FIELD(VAS_WINCTL_RX_WCRED_MODE, val);
1171 val = read_hvwc_reg(window, VREG(TX_WCRED));
1172 creds = GET_FIELD(VAS_TX_WCRED, val);
1174 val = read_hvwc_reg(window, VREG(LRX_WCRED));
1175 creds = GET_FIELD(VAS_LRX_WCRED, val);
1186 val = 0;
1212 u64 val;
1216 val = read_hvwc_reg(window, VREG(WIN_STATUS));
1217 busy = GET_FIELD(VAS_WIN_BUSY, val);
1219 val = 0;
1263 u64 val;
1265 val = read_hvwc_reg(window, VREG(WINCTL));
1266 val = SET_FIELD(VAS_WINCTL_PIN, val, 0);
1267 val = SET_FIELD(VAS_WINCTL_OPEN, val, 0);
1268 write_hvwc_reg(window, VREG(WINCTL), val);
1349 uint64_t val;
1351 val = 0ULL;
1353 val = SET_FIELD(VAS_TX_WCRED, val, 1);
1354 write_hvwc_reg(window, VREG(TX_WCRED_ADDER), val);
1356 val = SET_FIELD(VAS_LRX_WCRED, val, 1);
1357 write_hvwc_reg(window, VREG(LRX_WCRED_ADDER), val);