Lines Matching refs:pe
51 static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable);
54 void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level,
66 if (pe->flags & PNV_IODA_PE_DEV)
67 strscpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix));
68 else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
70 pci_domain_nr(pe->pbus), pe->pbus->number);
72 else if (pe->flags & PNV_IODA_PE_VF)
74 pci_domain_nr(pe->parent_dev->bus),
75 (pe->rid & 0xff00) >> 8,
76 PCI_SLOT(pe->rid), PCI_FUNC(pe->rid));
80 level, pfix, pe->pe_number, &vaf);
158 int run = 0, pe, i;
163 for (pe = phb->ioda.total_pe_num - 1; pe >= 0; pe--) {
164 if (test_bit(pe, phb->ioda.pe_alloc)) {
176 for (i = pe; i < pe + count; i++) {
180 ret = &phb->ioda.pe_array[pe];
187 void pnv_ioda_free_pe(struct pnv_ioda_pe *pe)
189 struct pnv_phb *phb = pe->phb;
190 unsigned int pe_num = pe->pe_number;
192 WARN_ON(pe->pdev);
193 memset(pe, 0, sizeof(struct pnv_ioda_pe));
298 struct pnv_ioda_pe *master_pe, *pe;
336 pe = &phb->ioda.pe_array[i];
338 phb->ioda.m64_segmap[pe->pe_number] = pe->pe_number;
340 pe->flags |= PNV_IODA_PE_MASTER;
341 INIT_LIST_HEAD(&pe->slaves);
342 master_pe = pe;
344 pe->flags |= PNV_IODA_PE_SLAVE;
345 pe->master = master_pe;
346 list_add_tail(&pe->list, &master_pe->slaves);
443 struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no];
448 if (pe->flags & PNV_IODA_PE_SLAVE) {
449 pe = pe->master;
450 if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)))
453 pe_no = pe->pe_number;
467 if (!(pe->flags & PNV_IODA_PE_MASTER))
470 list_for_each_entry(slave, &pe->slaves, list) {
483 struct pnv_ioda_pe *pe, *slave;
487 pe = &phb->ioda.pe_array[pe_no];
488 if (pe->flags & PNV_IODA_PE_SLAVE) {
489 pe = pe->master;
490 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
491 pe_no = pe->pe_number;
502 if (!(pe->flags & PNV_IODA_PE_MASTER))
506 list_for_each_entry(slave, &pe->slaves, list) {
523 struct pnv_ioda_pe *slave, *pe;
536 pe = &phb->ioda.pe_array[pe_no];
537 if (pe->flags & PNV_IODA_PE_SLAVE) {
538 pe = pe->master;
539 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
540 pe_no = pe->pe_number;
555 if (!(pe->flags & PNV_IODA_PE_MASTER))
558 list_for_each_entry(slave, &pe->slaves, list) {
643 struct pnv_ioda_pe *pe,
655 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
657 if (pe->flags & PNV_IODA_PE_MASTER) {
658 list_for_each_entry(slave, &pe->slaves, list)
671 ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add);
676 if (pe->flags & PNV_IODA_PE_MASTER) {
677 list_for_each_entry(slave, &pe->slaves, list) {
678 ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add);
684 if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS))
685 pdev = pe->pbus->self;
686 else if (pe->flags & PNV_IODA_PE_DEV)
687 pdev = pe->pdev->bus->self;
689 else if (pe->flags & PNV_IODA_PE_VF)
690 pdev = pe->parent_dev;
698 ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add);
710 struct pnv_ioda_pe *pe,
720 pe->pe_number,
727 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
731 rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number,
732 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN);
734 pe_warn(pe, "OPAL error %lld remove self from PELTV\n", rc);
737 int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
745 if (pe->pbus) {
750 parent = pe->pbus->self;
751 if (pe->flags & PNV_IODA_PE_BUS_ALL)
752 count = resource_size(&pe->pbus->busn_res);
764 dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
769 rid_end = pe->rid + (count << 8);
772 if (pe->flags & PNV_IODA_PE_VF)
773 parent = pe->parent_dev;
776 parent = pe->pdev->bus->self;
780 rid_end = pe->rid + 1;
784 for (rid = pe->rid; rid < rid_end; rid++)
792 pnv_ioda_unset_peltv(phb, pe, parent);
794 rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
797 pe_err(pe, "OPAL error %lld trying to setup PELT table\n", rc);
799 pe->pbus = NULL;
800 pe->pdev = NULL;
802 pe->parent_dev = NULL;
808 int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
814 if (pe->pbus) {
819 if (pe->flags & PNV_IODA_PE_BUS_ALL)
820 count = resource_size(&pe->pbus->busn_res);
832 dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
837 rid_end = pe->rid + (count << 8);
842 rid_end = pe->rid + 1;
851 rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
854 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);
863 pnv_ioda_set_peltv(phb, pe, true);
866 for (rid = pe->rid; rid < rid_end; rid++)
867 phb->ioda.pe_rmap[rid] = pe->pe_number;
869 pe->mve_number = 0;
878 struct pnv_ioda_pe *pe;
888 pe = pnv_ioda_alloc_pe(phb, 1);
889 if (!pe) {
901 pdn->pe_number = pe->pe_number;
902 pe->flags = PNV_IODA_PE_DEV;
903 pe->pdev = dev;
904 pe->pbus = NULL;
905 pe->mve_number = -1;
906 pe->rid = dev->bus->number << 8 | pdn->devfn;
907 pe->device_count++;
909 pe_info(pe, "Associated device to PE\n");
911 if (pnv_ioda_configure_pe(phb, pe)) {
913 pnv_ioda_free_pe(pe);
915 pe->pdev = NULL;
921 list_add_tail(&pe->list, &phb->ioda.pe_list);
923 return pe;
935 struct pnv_ioda_pe *pe = NULL;
944 pe = &phb->ioda.pe_array[pe_num];
950 pe = &phb->ioda.pe_array[phb->ioda.root_pe_idx];
953 if (!pe)
954 pe = pnv_ioda_pick_m64_pe(bus, all);
957 if (!pe)
958 pe = pnv_ioda_alloc_pe(phb, 1);
960 if (!pe) {
966 pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS);
967 pe->pbus = bus;
968 pe->pdev = NULL;
969 pe->mve_number = -1;
970 pe->rid = bus->busn_res.start << 8;
973 pe_info(pe, "Secondary bus %pad..%pad associated with PE#%x\n",
975 pe->pe_number);
977 pe_info(pe, "Secondary bus %pad associated with PE#%x\n",
978 &bus->busn_res.start, pe->pe_number);
980 if (pnv_ioda_configure_pe(phb, pe)) {
982 pnv_ioda_free_pe(pe);
983 pe->pbus = NULL;
988 list_add_tail(&pe->list, &phb->ioda.pe_list);
990 return pe;
997 struct pnv_ioda_pe *pe;
1000 pe = pnv_pci_bdfn_to_pe(phb, pci_dev_id(pdev));
1001 if (!pe) {
1007 pe = pnv_pci_bdfn_to_pe(phb, pci_dev_id(pdev));
1008 pci_info(pdev, "Configured PE#%x\n", pe ? pe->pe_number : 0xfffff);
1015 if (WARN_ON(!pe))
1018 pci_info(pdev, "Added to existing PE#%x\n", pe->pe_number);
1025 if (!pe->dma_setup_done && !pci_is_bridge(pdev)) {
1028 pnv_pci_ioda2_setup_dma_pe(phb, pe);
1037 pdn->pe_number = pe->pe_number;
1038 pe->device_count++;
1041 pdev->dev.archdata.dma_offset = pe->tce_bypass_base;
1042 set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]);
1045 if (pe->table_group.group)
1046 iommu_add_device(&pe->table_group, &pdev->dev);
1066 static int pnv_pci_ioda_dma_64bit_bypass(struct pnv_ioda_pe *pe)
1085 table_pages = alloc_pages_node(pe->phb->hose->node, GFP_KERNEL,
1101 rc = opal_pci_map_pe_dma_window(pe->phb->opal_id,
1102 pe->pe_number,
1104 (pe->pe_number << 1) + 0,
1110 pe_info(pe, "Using 64-bit DMA iommu bypass (through TVE#0)\n");
1114 pe_err(pe, "Error configuring 64-bit DMA bypass\n");
1123 struct pnv_ioda_pe *pe;
1128 pe = &phb->ioda.pe_array[pdn->pe_number];
1129 if (pe->tce_bypass_enabled) {
1130 u64 top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1;
1143 /* pe->pdev should be set if it's a single device, pe->pbus if not */
1144 (pe->device_count == 1 || !pe->pbus) &&
1147 s64 rc = pnv_pci_ioda_dma_64bit_bypass(pe);
1176 static inline void pnv_pci_phb3_tce_invalidate_pe(struct pnv_ioda_pe *pe)
1179 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb);
1180 unsigned long val = PHB3_TCE_KILL_INVAL_PE | (pe->pe_number & 0xFF);
1186 static void pnv_pci_phb3_tce_invalidate(struct pnv_ioda_pe *pe,
1190 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb);
1195 start |= (pe->pe_number & 0xFF);
1210 static inline void pnv_pci_ioda2_tce_invalidate_pe(struct pnv_ioda_pe *pe)
1212 struct pnv_phb *phb = pe->phb;
1215 pnv_pci_phb3_tce_invalidate_pe(pe);
1218 pe->pe_number, 0, 0, 0);
1227 struct pnv_ioda_pe *pe = container_of(tgl->table_group,
1229 struct pnv_phb *phb = pe->phb;
1233 pnv_pci_phb3_tce_invalidate(pe, shift,
1238 pe->pe_number, 1u << shift,
1280 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
1282 struct pnv_phb *phb = pe->phb;
1289 pe_info(pe, "Setting up window#%d %llx..%llx pg=%lx\n",
1298 pe->pe_number,
1299 (pe->pe_number << 1) + num,
1305 pe_err(pe, "Failed to configure TCE table, err %lld\n", rc);
1310 tbl, &pe->table_group);
1311 pnv_pci_ioda2_tce_invalidate_pe(pe);
1316 static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable)
1318 uint16_t window_id = (pe->pe_number << 1 ) + 1;
1321 pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis");
1326 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
1327 pe->pe_number,
1329 pe->tce_bypass_base,
1332 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
1333 pe->pe_number,
1335 pe->tce_bypass_base,
1339 pe_err(pe, "OPAL error %lld configuring bypass window\n", rc);
1341 pe->tce_bypass_enabled = enable;
1348 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
1350 int nid = pe->phb->hose->node;
1351 __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start;
1374 static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe)
1416 rc = pnv_pci_ioda2_create_table(&pe->table_group, 0, PAGE_SHIFT,
1419 pe_err(pe, "Failed to create 32-bit TCE table, err %ld",
1427 if (window_size > pe->phb->ioda.m32_pci_base) {
1428 res_start = pe->phb->ioda.m32_pci_base >> tbl->it_page_shift;
1432 tbl->it_index = (pe->phb->hose->global_number << 16) | pe->pe_number;
1433 if (iommu_init_table(tbl, pe->phb->hose->node, res_start, res_end))
1434 rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl);
1438 pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n", rc);
1443 pnv_pci_ioda2_set_bypass(pe, true);
1450 if (pe->pdev)
1451 set_iommu_table_base(&pe->pdev->dev, tbl);
1459 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
1461 struct pnv_phb *phb = pe->phb;
1464 pe_info(pe, "Removing DMA window #%d\n", num);
1466 ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,
1467 (pe->pe_number << 1) + num,
1471 pe_warn(pe, "Unmapping failed, ret = %ld\n", ret);
1473 pnv_pci_ioda2_tce_invalidate_pe(pe);
1527 static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, struct pci_bus *bus)
1532 set_iommu_table_base(&dev->dev, pe->table_group.tables[0]);
1533 dev->dev.archdata.dma_offset = pe->tce_bypass_base;
1535 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
1536 pnv_ioda_setup_bus_dma(pe, dev->subordinate);
1542 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
1545 struct iommu_table *tbl = pe->table_group.tables[0];
1554 pnv_pci_ioda2_set_bypass(pe, false);
1555 pnv_pci_ioda2_unset_window(&pe->table_group, 0);
1556 if (pe->pbus)
1557 pnv_ioda_setup_bus_dma(pe, pe->pbus);
1558 else if (pe->pdev)
1559 set_iommu_table_base(&pe->pdev->dev, NULL);
1567 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
1571 if (pe->table_group.tables[0])
1573 pnv_pci_ioda2_setup_default_config(pe);
1574 if (pe->pbus)
1575 pnv_ioda_setup_bus_dma(pe, pe->pbus);
1589 struct pnv_ioda_pe *pe)
1594 pe->tce_bypass_base = 1ull << 59;
1597 pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n",
1601 pe->table_group.tce32_start = 0;
1602 pe->table_group.tce32_size = phb->ioda.m32_pci_base;
1603 pe->table_group.max_dynamic_windows_supported =
1605 pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS;
1606 pe->table_group.pgsizes = pnv_ioda_parse_tce_sizes(phb);
1608 rc = pnv_pci_ioda2_setup_default_config(pe);
1613 pe->table_group.ops = &pnv_pci_ioda2_ops;
1614 iommu_register_group(&pe->table_group, phb->hose->global_number,
1615 pe->pe_number);
1617 pe->dma_setup_done = true;
1694 struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev);
1702 if (pe == NULL)
1706 if (pe->mve_number < 0)
1714 rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num);
1724 rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1,
1736 rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1,
1981 static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe *pe,
1984 struct pnv_phb *phb = pe->phb;
2000 phb->ioda.io_segmap[index] = pe->pe_number;
2002 pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index);
2005 __func__, rc, index, pe->pe_number);
2024 phb->ioda.m32_segmap[index] = pe->pe_number;
2026 pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index);
2029 __func__, rc, index, pe->pe_number);
2044 static void pnv_ioda_setup_pe_seg(struct pnv_ioda_pe *pe)
2054 BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)));
2056 list_for_each_entry(pdev, &pe->pbus->devices, bus_list) {
2058 pnv_ioda_setup_pe_res(pe, &pdev->resource[i]);
2065 if (!(pe->flags & PNV_IODA_PE_BUS_ALL) || !pci_is_bridge(pdev))
2068 pnv_ioda_setup_pe_res(pe,
2099 struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_num];
2104 pe_warn(pe, "rid: %04x dev count: %2d flags: %s%s%s%s%s%s\n",
2105 pe->rid, pe->device_count,
2106 (pe->flags & PNV_IODA_PE_DEV) ? "dev " : "",
2107 (pe->flags & PNV_IODA_PE_BUS) ? "bus " : "",
2108 (pe->flags & PNV_IODA_PE_BUS_ALL) ? "all " : "",
2109 (pe->flags & PNV_IODA_PE_MASTER) ? "master " : "",
2110 (pe->flags & PNV_IODA_PE_SLAVE) ? "slave " : "",
2111 (pe->flags & PNV_IODA_PE_VF) ? "vf " : "");
2293 struct pnv_ioda_pe *pe;
2310 pe = pnv_ioda_setup_bus_PE(bus, all);
2311 if (!pe)
2314 pnv_ioda_setup_pe_seg(pe);
2341 struct pnv_ioda_pe *pe;
2348 pe = pnv_ioda_setup_dev_PE(dev);
2349 if (!pe)
2355 void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe *pe)
2357 struct iommu_table *tbl = pe->table_group.tables[0];
2360 if (!pe->dma_setup_done)
2363 rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0);
2365 pe_warn(pe, "OPAL error %lld release DMA window\n", rc);
2367 pnv_pci_ioda2_set_bypass(pe, false);
2368 if (pe->table_group.group) {
2369 iommu_group_put(pe->table_group.group);
2370 WARN_ON(pe->table_group.group);
2376 static void pnv_ioda_free_pe_seg(struct pnv_ioda_pe *pe,
2380 struct pnv_phb *phb = pe->phb;
2385 if (map[idx] != pe->pe_number)
2392 pe_warn(pe, "Error %lld unmapping (%d) segment#%d\n",
2399 static void pnv_ioda_release_pe_seg(struct pnv_ioda_pe *pe)
2401 struct pnv_phb *phb = pe->phb;
2404 pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE,
2409 static void pnv_ioda_release_pe(struct pnv_ioda_pe *pe)
2411 struct pnv_phb *phb = pe->phb;
2414 pe_info(pe, "Releasing PE\n");
2417 list_del(&pe->list);
2422 pnv_pci_ioda2_release_pe_dma(pe);
2430 pnv_ioda_release_pe_seg(pe);
2431 pnv_ioda_deconfigure_pe(pe->phb, pe);
2434 if (pe->flags & PNV_IODA_PE_MASTER) {
2435 list_for_each_entry_safe(slave, tmp, &pe->slaves, list) {
2447 if (phb->ioda.root_pe_idx == pe->pe_number)
2450 pnv_ioda_free_pe(pe);
2457 struct pnv_ioda_pe *pe;
2484 pe = &phb->ioda.pe_array[pdn->pe_number];
2487 WARN_ON(--pe->device_count < 0);
2488 if (pe->device_count == 0)
2489 pnv_ioda_release_pe(pe);
2503 struct pnv_ioda_pe *pe;
2505 list_for_each_entry(pe, &phb->ioda.pe_list, list) {
2506 if (!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)))
2509 if (!pe->pbus)
2512 if (bus->number == ((pe->rid >> 8) & 0xFF)) {
2513 pe->pbus = bus;
2524 struct pnv_ioda_pe *pe;
2529 pe = pnv_pci_bdfn_to_pe(phb, pci_dev_id(pdev));
2530 if (!pe)
2533 if (!pe->table_group.group)
2536 return iommu_group_ref_get(pe->table_group.group);
2658 prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL);