Lines Matching refs:reset
391 * should be blocked until PE reset. MMIO access is dropped
418 * to PE reset.
576 * reset is completed. In order to keep EEH core
578 * state during PE reset.
728 /* Issue PHB complete reset request */
743 * successfully. The PHB reset is usually PHB complete
744 * reset followed by hot reset on root bus. So we also
771 * During the reset deassert time, we needn't care
772 * the reset scope because the firmware does nothing
773 * for fundamental or hot reset during deassert phase.
862 /* Hot reset to the bus if firmware cannot handle */
863 if (!dn || !of_get_property(dn, "ibm,reset-by-firmware", NULL))
866 pr_debug("%s: FW reset PCI bus %04x:%02x with option %d\n",
880 dev_dbg(&pdev->dev, "%s: Unsupported reset %d\n",
1025 * @option: reset option
1027 * Do reset on the indicated PE. For PCI bus sensitive PE,
1028 * we need to reset the parent p2p bridge. The PHB has to
1030 * PCI device sensitive PE, we will try to reset the device
1032 * reset yet, so all reset would be SOFT (HOT) reset.
1042 * For PHB reset, we always have complete reset. For those PEs whose
1044 * (usually bus#1), we apply hot or fundamental reset on the root port.
1045 * For other PEs, we always have hot reset on the PE primary bus.
1048 * frozen state during PE reset. However, the good idea here from
1049 * benh is to keep frozen state before we get PE reset done completely
1052 * reset. The side effect is that EEH core has to clear the frozen
1093 * For hot resets try use the generic PCI error recovery reset
1096 * reset methods to prevent spurious hotplug events during the reset.
1099 * PCI core doesn't really have a concept of a fundamental reset,
1106 * de-assert step. It's like the OPAL reset API was
1117 /* otherwise, use the generic bridge reset. this might call into FW */
1632 .reset = pnv_eeh_reset,