Lines Matching refs:val

43 #define READ_SHADOW_REG(val, reg)				\
47 (val) = shadow_regs->reg; \
50 #define READ_MMIO_UPPER32(val, reg) \
54 (val) = (u32)(in_be64(&pmd_regs->reg) >> 32); \
64 u32 val_in_latch, val = 0;
71 READ_SHADOW_REG(val, pm_ctr[phys_ctr]);
73 READ_MMIO_UPPER32(val, pm_ctr[phys_ctr]);
77 return val;
81 void cbe_write_phys_ctr(u32 cpu, u32 phys_ctr, u32 val)
91 WRITE_WO_MMIO(pm_ctr[phys_ctr], val);
116 u32 val;
119 val = cbe_read_phys_ctr(cpu, phys_ctr);
122 val = (ctr < NR_PHYS_CTRS) ? (val >> 16) : (val & 0xffff);
124 return val;
128 void cbe_write_ctr(u32 cpu, u32 ctr, u32 val)
139 val = (val << 16) | (phys_val & 0xffff);
141 val = (val & 0xffff) | (phys_val & 0xffff0000);
144 cbe_write_phys_ctr(cpu, phys_ctr, val);
164 void cbe_write_pm07_control(u32 cpu, u32 ctr, u32 val)
167 WRITE_WO_MMIO(pm07_control[ctr], val);
177 u32 val = 0;
181 READ_SHADOW_REG(val, group_control);
185 READ_SHADOW_REG(val, debug_bus_control);
189 READ_MMIO_UPPER32(val, trace_address);
193 READ_SHADOW_REG(val, ext_tr_timer);
197 READ_MMIO_UPPER32(val, pm_status);
201 READ_SHADOW_REG(val, pm_control);
205 READ_MMIO_UPPER32(val, pm_interval);
209 READ_SHADOW_REG(val, pm_start_stop);
213 return val;
217 void cbe_write_pm(u32 cpu, enum pm_reg_name reg, u32 val)
221 WRITE_WO_MMIO(group_control, val);
225 WRITE_WO_MMIO(debug_bus_control, val);
229 WRITE_WO_MMIO(trace_address, val);
233 WRITE_WO_MMIO(ext_tr_timer, val);
237 WRITE_WO_MMIO(pm_status, val);
241 WRITE_WO_MMIO(pm_control, val);
245 WRITE_WO_MMIO(pm_interval, val);
249 WRITE_WO_MMIO(pm_start_stop, val);