Lines Matching refs:port
655 int (*port_init_hw)(struct ppc4xx_pciex_port *port);
656 int (*setup_utl)(struct ppc4xx_pciex_port *port);
657 void (*check_link)(struct ppc4xx_pciex_port *port);
662 static int __init ppc4xx_pciex_wait_on_sdr(struct ppc4xx_pciex_port *port,
671 val = mfdcri(SDR0, port->sdr_base + sdr_offset);
674 port->index, sdr_offset, timeout_ms, val);
682 static int __init ppc4xx_pciex_port_reset_sdr(struct ppc4xx_pciex_port *port)
685 if (ppc4xx_pciex_wait_on_sdr(port, PESDRn_RCSSTS, 1 << 20, 0, 10)) {
687 port->index);
694 static void __init ppc4xx_pciex_check_link_sdr(struct ppc4xx_pciex_port *port)
696 printk(KERN_INFO "PCIE%d: Checking link...\n", port->index);
705 if (!port->has_ibpre ||
706 !ppc4xx_pciex_wait_on_sdr(port, PESDRn_LOOP,
710 port->index);
711 if (ppc4xx_pciex_wait_on_sdr(port, PESDRn_LOOP,
714 "PCIE%d: Link up failed\n", port->index);
717 "PCIE%d: link is up !\n", port->index);
718 port->link = 1;
721 printk(KERN_INFO "PCIE%d: No device detected.\n", port->index);
841 static int __init ppc440spe_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
845 if (port->endpoint)
850 if (port->index == 0)
855 mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val);
856 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x20222222);
858 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x11000000);
859 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL0SET1, 0x35000000);
860 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL1SET1, 0x35000000);
861 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL2SET1, 0x35000000);
862 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL3SET1, 0x35000000);
863 if (port->index == 0) {
864 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL4SET1,
866 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL5SET1,
868 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL6SET1,
870 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL7SET1,
873 dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET,
876 return ppc4xx_pciex_port_reset_sdr(port);
879 static int __init ppc440speA_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
881 return ppc440spe_pciex_init_port_hw(port);
884 static int __init ppc440speB_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
886 int rc = ppc440spe_pciex_init_port_hw(port);
888 port->has_ibpre = 1;
893 static int ppc440speA_pciex_init_utl(struct ppc4xx_pciex_port *port)
896 dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x68782800);
901 out_be32(port->utl_base + PEUTL_OUTTR, 0x08000000);
902 out_be32(port->utl_base + PEUTL_INTR, 0x02000000);
903 out_be32(port->utl_base + PEUTL_OPDBSZ, 0x10000000);
904 out_be32(port->utl_base + PEUTL_PBBSZ, 0x53000000);
905 out_be32(port->utl_base + PEUTL_IPHBSZ, 0x08000000);
906 out_be32(port->utl_base + PEUTL_IPDBSZ, 0x10000000);
907 out_be32(port->utl_base + PEUTL_RCIRQEN, 0x00f00000);
908 out_be32(port->utl_base + PEUTL_PCTL, 0x80800066);
913 static int ppc440speB_pciex_init_utl(struct ppc4xx_pciex_port *port)
916 out_be32(port->utl_base + PEUTL_PBCTL, 0x08000000);
945 static int __init ppc460ex_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
950 if (port->endpoint)
955 if (port->index == 0) {
963 mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val);
964 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, utlset1);
965 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01210000);
967 switch (port->index) {
994 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
995 mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) |
1000 switch (port->index) {
1011 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
1012 (mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) &
1016 port->has_ibpre = 1;
1018 return ppc4xx_pciex_port_reset_sdr(port);
1021 static int ppc460ex_pciex_init_utl(struct ppc4xx_pciex_port *port)
1023 dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x0);
1028 out_be32(port->utl_base + PEUTL_PBCTL, 0x0800000c);
1029 out_be32(port->utl_base + PEUTL_OUTTR, 0x08000000);
1030 out_be32(port->utl_base + PEUTL_INTR, 0x02000000);
1031 out_be32(port->utl_base + PEUTL_OPDBSZ, 0x04000000);
1032 out_be32(port->utl_base + PEUTL_PBBSZ, 0x00000000);
1033 out_be32(port->utl_base + PEUTL_IPHBSZ, 0x02000000);
1034 out_be32(port->utl_base + PEUTL_IPDBSZ, 0x04000000);
1035 out_be32(port->utl_base + PEUTL_RCIRQEN,0x00f00000);
1036 out_be32(port->utl_base + PEUTL_PCTL, 0x80800066);
1052 /* Return the number of pcie port */
1056 static int __init apm821xx_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
1065 * PT quad port, SAS LSI 1064E)
1071 if (port->endpoint)
1078 mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val);
1079 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x00000000);
1080 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01010000);
1090 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
1091 mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) |
1095 val = PESDR0_460EX_RSTSTA - port->sdr_base;
1096 if (ppc4xx_pciex_wait_on_sdr(port, val, 0x1, 1, 100)) {
1100 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
1101 (mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) &
1105 port->has_ibpre = 1;
1191 * third PCIe port
1204 static int __init ppc460sx_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
1207 if (port->endpoint)
1208 dcri_clrset(SDR0, port->sdr_base + PESDRn_UTLSET2,
1211 dcri_clrset(SDR0, port->sdr_base + PESDRn_UTLSET2,
1214 dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET,
1218 port->has_ibpre = 1;
1220 return ppc4xx_pciex_port_reset_sdr(port);
1223 static int ppc460sx_pciex_init_utl(struct ppc4xx_pciex_port *port)
1226 out_be32 (port->utl_base + PEUTL_PBBSZ, 0x00000000);
1228 out_be32(port->utl_base + PEUTL_PCTL, 0x80800000);
1232 static void __init ppc460sx_pciex_check_link(struct ppc4xx_pciex_port *port)
1237 port->link = 0;
1239 mbase = ioremap(port->cfg_space.start + 0x10000000, 0x1000);
1242 port->node);
1252 port->link = 1;
1274 static void __init ppc405ex_pcie_phy_reset(struct ppc4xx_pciex_port *port)
1277 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01010000);
1281 if (port->endpoint)
1282 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01111000);
1284 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01101000);
1288 while (!(mfdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSTA) & 0x00001000))
1292 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x00101000);
1295 static int __init ppc405ex_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
1299 if (port->endpoint)
1304 mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET,
1307 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x00000000);
1308 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01010000);
1309 mtdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSET1, 0x720F0000);
1310 mtdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSET2, 0x70600003);
1319 val = mfdcri(SDR0, port->sdr_base + PESDRn_LOOP);
1321 ppc405ex_pcie_phy_reset(port);
1323 dcr_write(port->dcrs, DCRO_PEGPL_CFG, 0x10000000); /* guarded on */
1325 port->has_ibpre = 1;
1327 return ppc4xx_pciex_port_reset_sdr(port);
1330 static int ppc405ex_pciex_init_utl(struct ppc4xx_pciex_port *port)
1332 dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x0);
1337 out_be32(port->utl_base + PEUTL_OUTTR, 0x02000000);
1338 out_be32(port->utl_base + PEUTL_INTR, 0x02000000);
1339 out_be32(port->utl_base + PEUTL_OPDBSZ, 0x04000000);
1340 out_be32(port->utl_base + PEUTL_PBBSZ, 0x21000000);
1341 out_be32(port->utl_base + PEUTL_IPHBSZ, 0x02000000);
1342 out_be32(port->utl_base + PEUTL_IPDBSZ, 0x04000000);
1343 out_be32(port->utl_base + PEUTL_RCIRQEN, 0x00f00000);
1344 out_be32(port->utl_base + PEUTL_PCTL, 0x80800066);
1346 out_be32(port->utl_base + PEUTL_PBCTL, 0x08000000);
1368 static void __init ppc_476fpe_pciex_check_link(struct ppc4xx_pciex_port *port)
1372 void __iomem *mbase = ioremap(port->cfg_space.start + 0x10000000,
1375 printk(KERN_INFO "PCIE%d: Checking link...\n", port->index);
1379 port->index);
1392 printk(KERN_INFO "PCIE%d: link is up !\n", port->index);
1393 port->link = 1;
1395 printk(KERN_WARNING "PCIE%d: Link up failed\n", port->index);
1459 static void __init ppc4xx_pciex_port_init_mapping(struct ppc4xx_pciex_port *port)
1462 dcr_write(port->dcrs, DCRO_PEGPL_CFGBAH,
1463 RES_TO_U32_HIGH(port->cfg_space.start));
1464 dcr_write(port->dcrs, DCRO_PEGPL_CFGBAL,
1465 RES_TO_U32_LOW(port->cfg_space.start));
1468 dcr_write(port->dcrs, DCRO_PEGPL_CFGMSK, 0xe0000001);
1471 dcr_write(port->dcrs, DCRO_PEGPL_REGBAH,
1472 RES_TO_U32_HIGH(port->utl_regs.start));
1473 dcr_write(port->dcrs, DCRO_PEGPL_REGBAL,
1474 RES_TO_U32_LOW(port->utl_regs.start));
1477 dcr_write(port->dcrs, DCRO_PEGPL_REGMSK, 0x00007001);
1480 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL, 0);
1481 dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKL, 0);
1482 dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKL, 0);
1483 dcr_write(port->dcrs, DCRO_PEGPL_MSGMSK, 0);
1486 static int __init ppc4xx_pciex_port_init(struct ppc4xx_pciex_port *port)
1492 rc = ppc4xx_pciex_hwops->port_init_hw(port);
1500 ppc4xx_pciex_port_init_mapping(port);
1503 ppc4xx_pciex_hwops->check_link(port);
1508 port->utl_base = ioremap(port->utl_regs.start, 0x100);
1509 BUG_ON(port->utl_base == NULL);
1515 ppc4xx_pciex_hwops->setup_utl(port);
1520 if (port->sdr_base) {
1521 if (of_device_is_compatible(port->node,
1523 if (port->link && ppc4xx_pciex_wait_on_sdr(port,
1527 port->index);
1528 port->link = 0;
1530 } else if (port->link &&
1531 ppc4xx_pciex_wait_on_sdr(port, PESDRn_RCSSTS,
1534 port->index);
1535 port->link = 0;
1538 dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET, 0, 1 << 20);
1546 static int ppc4xx_pciex_validate_bdf(struct ppc4xx_pciex_port *port,
1553 if (port->endpoint && bus->number != port->hose->first_busno)
1557 if (bus->number > port->hose->last_busno) {
1567 if (bus->number == port->hose->first_busno && devfn != 0)
1571 if (bus->number == (port->hose->first_busno + 1) &&
1576 if ((bus->number != port->hose->first_busno) && !port->link)
1582 static void __iomem *ppc4xx_pciex_get_config_base(struct ppc4xx_pciex_port *port,
1591 if (bus->number == port->hose->first_busno)
1592 return (void __iomem *)port->hose->cfg_addr;
1594 relbus = bus->number - (port->hose->first_busno + 1);
1595 return (void __iomem *)port->hose->cfg_data +
1603 struct ppc4xx_pciex_port *port =
1608 BUG_ON(hose != port->hose);
1610 if (ppc4xx_pciex_validate_bdf(port, bus, devfn) != 0)
1613 addr = ppc4xx_pciex_get_config_base(port, bus, devfn);
1620 gpl_cfg = dcr_read(port->dcrs, DCRO_PEGPL_CFG);
1621 dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg | GPL_DMER_MASK_DISA);
1624 out_be32(port->utl_base + PEUTL_RCSTA, 0x00040000);
1644 if (in_be32(port->utl_base + PEUTL_RCSTA) & 0x00040000) {
1651 dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg);
1660 struct ppc4xx_pciex_port *port =
1665 if (ppc4xx_pciex_validate_bdf(port, bus, devfn) != 0)
1668 addr = ppc4xx_pciex_get_config_base(port, bus, devfn);
1675 gpl_cfg = dcr_read(port->dcrs, DCRO_PEGPL_CFG);
1676 dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg | GPL_DMER_MASK_DISA);
1695 dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg);
1706 static int __init ppc4xx_setup_one_pciex_POM(struct ppc4xx_pciex_port *port,
1737 dcr_write(port->dcrs, DCRO_PEGPL_OMR1BAH, lah);
1738 dcr_write(port->dcrs, DCRO_PEGPL_OMR1BAL, lal);
1739 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKH, 0x7fffffff);
1741 if (of_device_is_compatible(port->node, "ibm,plb-pciex-460sx"))
1742 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL,
1746 port->node, "ibm,plb-pciex-476fpe") ||
1748 port->node, "ibm,plb-pciex-476gtr"))
1749 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL,
1753 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL,
1760 dcr_write(port->dcrs, DCRO_PEGPL_OMR2BAH, lah);
1761 dcr_write(port->dcrs, DCRO_PEGPL_OMR2BAL, lal);
1762 dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKH, 0x7fffffff);
1763 dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKL,
1769 dcr_write(port->dcrs, DCRO_PEGPL_OMR3BAH, lah);
1770 dcr_write(port->dcrs, DCRO_PEGPL_OMR3BAL, lal);
1771 dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKH, 0x7fffffff);
1773 dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKL,
1782 static void __init ppc4xx_configure_pciex_POMs(struct ppc4xx_pciex_port *port,
1798 port->node);
1803 if (ppc4xx_setup_one_pciex_POM(port, hose, mbase,
1821 if (ppc4xx_setup_one_pciex_POM(port, hose, mbase,
1831 ppc4xx_setup_one_pciex_POM(port, hose, mbase,
1836 static void __init ppc4xx_configure_pciex_PIMs(struct ppc4xx_pciex_port *port,
1844 if (port->endpoint) {
1877 if (of_device_is_compatible(port->node, "ibm,plb-pciex-460sx") ||
1879 port->node, "ibm,plb-pciex-476fpe") ||
1881 port->node, "ibm,plb-pciex-476gtr"))
1910 static void __init ppc4xx_pciex_port_setup_hose(struct ppc4xx_pciex_port *port)
1921 primary = of_property_read_bool(port->node, "primary");
1924 bus_range = of_get_property(port->node, "bus-range", NULL);
1927 hose = pcibios_alloc_controller(port->node);
1931 /* We stick the port number in "indirect_type" so the config space
1932 * ops can retrieve the port data structure easily
1934 hose->indirect_type = port->index;
1951 if (!port->endpoint) {
1955 cfg_data = ioremap(port->cfg_space.start +
1960 port->node);
1969 mbase = ioremap(port->cfg_space.start + 0x10000000, 0x1000);
1972 port->node);
1977 pr_debug("PCIE %pOF, bus %d..%d\n", port->node,
1984 port->hose = hose;
1987 if (!port->endpoint) {
1989 * Set bus numbers on our root port
2002 pci_process_bridge_OF_ranges(hose, port->node, primary);
2009 ppc4xx_configure_pciex_POMs(port, hose, mbase);
2012 ppc4xx_configure_pciex_PIMs(port, hose, mbase, &dma_window);
2022 pval = of_get_property(port->node, "vendor-id", NULL);
2026 if (!port->endpoint)
2027 val = 0xaaa0 + port->index;
2029 val = 0xeee0 + port->index;
2033 pval = of_get_property(port->node, "device-id", NULL);
2037 if (!port->endpoint)
2038 val = 0xbed0 + port->index;
2040 val = 0xfed0 + port->index;
2045 if (of_device_is_compatible(port->node, "ibm,plb-pciex-460sx"))
2048 if (!port->endpoint) {
2053 port->index);
2059 port->index);
2074 struct ppc4xx_pciex_port *port;
2085 /* Get the port number from the device-tree */
2086 pval = of_get_property(np, "port", NULL);
2088 printk(KERN_ERR "PCIE: Can't find port number for %pOF\n", np);
2093 printk(KERN_ERR "PCIE: port number out of range for %pOF\n",
2097 port = &ppc4xx_pciex_ports[portno];
2098 port->index = portno;
2104 printk(KERN_INFO "PCIE%d: Port disabled via device-tree\n", port->index);
2108 port->node = of_node_get(np);
2116 port->sdr_base = *pval;
2120 * Resulting from this setup this PCIe port will be configured
2123 if (of_node_is_type(port->node, "pci-endpoint")) {
2124 port->endpoint = 1;
2125 } else if (of_node_is_type(port->node, "pci")) {
2126 port->endpoint = 0;
2134 if (of_address_to_resource(np, 0, &port->cfg_space)) {
2139 if (of_address_to_resource(np, 1, &port->utl_regs)) {
2150 port->dcrs = dcr_map(np, dcrs, dcr_resource_len(np, 0));
2152 /* Initialize the port specific registers */
2153 if (ppc4xx_pciex_port_init(port)) {
2154 printk(KERN_WARNING "PCIE%d: Port init failed\n", port->index);
2159 ppc4xx_pciex_port_setup_hose(port);