Lines Matching defs:event
11 PMU_FORMAT_ATTR(event, "config:0-49");
45 static inline bool event_is_fab_match(u64 event)
48 event &= 0xff0fe;
51 return (event == 0x30056 || event == 0x4f052);
54 static bool is_event_valid(u64 event)
63 return !(event & ~valid_mask);
66 static inline bool is_event_marked(u64 event)
68 if (event & EVENT_IS_MARKED)
74 static unsigned long sdar_mod_val(u64 event)
77 return p10_SDAR_MODE(event);
79 return p9_SDAR_MODE(event);
82 static void mmcra_sdar_mode(u64 event, unsigned long *mmcra)
93 * Marked event: MMCRA[SDAR_MODE] will be set to 0b00 ('No Updates'),
96 * MMCRA[SDAR_MODE] will be set from event code.
97 * If sdar_mode from event is zero, default to 0b01. Hardware
101 if (is_event_marked(event) || (*mmcra & MMCRA_SAMPLE_ENABLE))
103 else if (sdar_mod_val(event))
104 *mmcra |= sdar_mod_val(event) << MMCRA_SDAR_MODE_SHIFT;
120 * Incase of P10, thresh_cmp value is not part of raw event code
164 static unsigned long combine_from_event(u64 event)
167 return p9_EVENT_COMBINE(event);
169 return EVENT_COMBINE(event);
180 static inline bool event_is_threshold(u64 event)
182 return (event >> EVENT_THR_SEL_SHIFT) & EVENT_THR_SEL_MASK;
185 static bool is_thresh_cmp_valid(u64 event)
190 return p10_thresh_cmp_val(event) >= 0;
197 cmp = (event >> EVENT_THR_CMP_SHIFT) & EVENT_THR_CMP_MASK;
206 static unsigned int dc_ic_rld_quad_l1_sel(u64 event)
210 cache = (event >> EVENT_CACHE_SEL_SHIFT) & MMCR1_DC_IC_QUAL_MASK;
401 int isa207_get_constraint(u64 event, unsigned long *maskp, unsigned long *valp, u64 event_config1)
408 if (!is_event_valid(event))
411 pmc = (event >> EVENT_PMC_SHIFT) & EVENT_PMC_MASK;
412 unit = (event >> EVENT_UNIT_SHIFT) & EVENT_UNIT_MASK;
414 cache = (event >> EVENT_CACHE_SEL_SHIFT) &
417 cache = (event >> EVENT_CACHE_SEL_SHIFT) &
419 ebb = (event >> EVENT_EBB_SHIFT) & EVENT_EBB_MASK;
427 /* Ignore Linux defined bits when checking event below */
428 base_event = event & ~EVENT_LINUX_MASK;
451 * Don't count events on PMC 5 & 6, there is only one valid event
462 value |= CNST_L2L3_GROUP_VAL(event >> p10_L2L3_EVENT_SHIFT);
466 value |= CNST_CACHE_GROUP_VAL(event & 0xff);
484 } else if (cpu_has_feature(CPU_FTR_ARCH_300) || (event & EVENT_IS_L1)) {
491 value |= CNST_RADIX_SCOPE_GROUP_VAL(event >> p10_EVENT_RADIX_SCOPE_QUAL_SHIFT);
494 if (is_event_marked(event)) {
496 value |= CNST_SAMPLE_VAL(event >> EVENT_SAMPLE_SHIFT);
500 if (event_is_threshold(event) && is_thresh_cmp_valid(event_config1)) {
502 value |= CNST_THRESH_CTL_SEL_VAL(event >> EVENT_THRESH_SHIFT);
505 } else if (event_is_threshold(event))
508 if (event_is_threshold(event) && is_thresh_cmp_valid(event)) {
510 value |= CNST_THRESH_VAL(event >> EVENT_THRESH_SHIFT);
511 } else if (event_is_threshold(event))
518 if (event_is_fab_match(event)) {
520 value |= CNST_FAB_MATCH_VAL(event >> EVENT_THR_CTL_SHIFT);
522 if (!is_thresh_cmp_valid(event))
526 value |= CNST_THRESH_VAL(event >> EVENT_THRESH_SHIFT);
535 if (event & EVENT_WANTS_BHRB) {
541 value |= CNST_IFM_VAL(event >> EVENT_IFM_SHIFT);
558 int isa207_compute_mmcr(u64 event[], int n_ev,
571 pmc = (event[i] >> EVENT_PMC_SHIFT) & EVENT_PMC_MASK;
587 pmc = (event[i] >> EVENT_PMC_SHIFT) & EVENT_PMC_MASK;
588 unit = (event[i] >> EVENT_UNIT_SHIFT) & EVENT_UNIT_MASK;
589 combine = combine_from_event(event[i]);
590 psel = event[i] & EVENT_PSEL_MASK;
608 mmcra_sdar_mode(event[i], &mmcra);
611 cache = dc_ic_rld_quad_l1_sel(event[i]);
614 if (event[i] & EVENT_IS_L1) {
615 cache = dc_ic_rld_quad_l1_sel(event[i]);
622 val = (event[i] >> p10_EVENT_RADIX_SCOPE_QUAL_SHIFT) &
627 if (is_event_marked(event[i])) {
630 val = (event[i] >> EVENT_SAMPLE_SHIFT) & EVENT_SAMPLE_MASK;
641 if (!cpu_has_feature(CPU_FTR_ARCH_300) && event_is_fab_match(event[i])) {
642 mmcr1 |= ((event[i] >> EVENT_THR_CTL_SHIFT) &
645 val = (event[i] >> EVENT_THR_CTL_SHIFT) & EVENT_THR_CTL_MASK;
647 val = (event[i] >> EVENT_THR_SEL_SHIFT) & EVENT_THR_SEL_MASK;
650 val = (event[i] >> EVENT_THR_CMP_SHIFT) &
661 val = (event[i] >> p10_L2L3_EVENT_SHIFT) &
666 if (event[i] & EVENT_WANTS_BHRB) {
667 val = (event[i] >> EVENT_IFM_SHIFT) & EVENT_IFM_MASK;
673 (has_branch_stack(pevents[i]) || (event[i] & EVENT_WANTS_BHRB)))
694 val = (event[i] >> p10_EVENT_MMCR3_SHIFT) &
739 static int find_alternative(u64 event, const unsigned int ev_alt[][MAX_ALT], int size)
744 if (event < ev_alt[i][0])
748 if (event == ev_alt[i][j])
755 int isa207_get_alternatives(u64 event, u64 alt[], int size, unsigned int flags,
761 alt[num_alt++] = event;
762 i = find_alternative(event, ev_alt, size);
764 /* Filter out the original event, it's already in alt[0] */
767 if (alt_event && alt_event != event)
803 u64 event = ev->attr.config;
805 val = (event >> EVENT_SAMPLE_SHIFT) & EVENT_SAMPLE_MASK;
835 val = (event >> EVENT_THR_CTL_SHIFT) & EVENT_THR_CTL_MASK;