Lines Matching defs:cache
208 unsigned int cache;
210 cache = (event >> EVENT_CACHE_SEL_SHIFT) & MMCR1_DC_IC_QUAL_MASK;
211 return cache;
403 unsigned int unit, pmc, cache, ebb;
414 cache = (event >> EVENT_CACHE_SEL_SHIFT) &
417 cache = (event >> EVENT_CACHE_SEL_SHIFT) &
471 } else if (cache & 0x7) {
473 * L2/L3 events contain a cache selector field, which is
478 * have a cache selector of zero. The bank selector (bit 3) is
486 value |= CNST_L1_QUAL_VAL(cache);
562 unsigned long mmcra, mmcr1, mmcr2, unit, combine, psel, cache, val;
611 cache = dc_ic_rld_quad_l1_sel(event[i]);
612 mmcr1 |= (cache) << MMCR1_DC_IC_QUAL_SHIFT;
615 cache = dc_ic_rld_quad_l1_sel(event[i]);
616 mmcr1 |= (cache) << MMCR1_DC_IC_QUAL_SHIFT;