Lines Matching refs:reg

593 	rn = op->reg;
645 	rn = op->reg;
739 				      int reg, bool cross_endian)
747 		err = do_lq(ea, &regs->gpr[reg]);
749 		err = read_mem(&regs->gpr[reg + IS_LE], ea, 8, regs);
751 			err = read_mem(&regs->gpr[reg + IS_BE], ea + 8, 8, regs);
754 		do_byte_reverse(&regs->gpr[reg], 16);
759 				       int reg, bool cross_endian)
766 	vals[0] = regs->gpr[reg];
767 	vals[1] = regs->gpr[reg + 1];
783 void emulate_vsx_load(struct instruction_op *op, union vsx_reg *reg,
793 	reg->d[0] = reg->d[1] = 0;
802 		memcpy(reg, mem, size);
806 			do_byte_reverse(reg, size);
812 		memcpy(&reg->b[i], mem, read_size);
814 			do_byte_reverse(&reg->b[i], 8);
818 				reg->d[IS_LE] = (signed int) reg->d[IS_LE];
821 				conv_sp_to_dp(&reg->fp[1 + IS_LE],
822 					      &reg->dp[IS_LE]);
828 				reg->d[IS_BE] = !rev ? v : byterev_8(v);
830 				reg->d[IS_BE] = reg->d[IS_LE];
838 			reg->w[i] = !rev ? *wp++ : byterev_4(*wp++);
841 			u32 val = reg->w[IS_LE ? 3 : 0];
844 				reg->w[i] = val;
853 			reg->h[i] = !rev ? *hp++ : byterev_2(*hp++);
861 			reg->b[i] = *bp++;
869 void emulate_vsx_store(struct instruction_op *op, const union vsx_reg *reg,
889 			buf32[0].d[0] = byterev_8(reg[1].d[1]);
890 			buf32[0].d[1] = byterev_8(reg[1].d[0]);
891 			buf32[1].d[0] = byterev_8(reg[0].d[1]);
892 			buf32[1].d[1] = byterev_8(reg[0].d[0]);
895 			memcpy(mem, reg, size);
906 			buf.d[0] = byterev_8(reg->d[1]);
907 			buf.d[1] = byterev_8(reg->d[0]);
908 			reg = &buf;
910 		memcpy(mem, reg, size);
919 			conv_dp_to_sp(&reg->dp[IS_LE], &buf.fp[1 + IS_LE]);
921 			reg = &buf;
923 		memcpy(mem, &reg->b[i], write_size);
925 			memcpy(mem + 8, &reg->d[IS_BE], 8);
937 			*wp++ = !rev ? reg->w[i] : byterev_4(reg->w[i]);
945 			*hp++ = !rev ? reg->h[i] : byterev_2(reg->h[i]);
953 			*bp++ = reg->b[i];
965 	int reg = op->reg;
977 	if (reg < 32) {
982 				load_vsrn(reg + i, &buf[j].v);
987 				current->thread.fp_state.fpr[reg + i][0] = buf[j].d[0];
988 				current->thread.fp_state.fpr[reg + i][1] = buf[j].d[1];
995 				load_vsrn(reg + i, &buf[j].v);
1000 				current->thread.vr_state.vr[reg - 32 + i] = buf[j].v;
1012 	int reg = op->reg;
1023 	if (reg < 32) {
1028 				store_vsrn(reg + i, &buf[j].v);
1033 				buf[j].d[0] = current->thread.fp_state.fpr[reg + i][0];
1034 				buf[j].d[1] = current->thread.fp_state.fpr[reg + i][1];
1041 				store_vsrn(reg + i, &buf[j].v);
1046 				buf[j].v = current->thread.vr_state.vr[reg - 32 + i];
1177 	op->reg = rd;
1498 		op->reg = rd;
1748 			op->reg = rd;
1754 			op->reg = rd;
1762 			op->reg = rd;
1821 			op->reg = rd;
2252 			op->reg = rd;
2258 			op->reg = rd;
2279 	op->reg = rd;
2534 			op->reg = rd | ((word & 1) << 5);
2540 			op->reg = rd | ((word & 1) << 5);
2546 			op->reg = rd | ((word & 1) << 5);
2554 			op->reg = rd | ((word & 1) << 5);
2565 			op->reg = rd | ((word & 1) << 5);
2577 			op->reg = rd | ((word & 1) << 5);
2586 			op->reg = VSX_REGISTER_XTP(rd);
2594 			op->reg = rd | ((word & 1) << 5);
2603 			op->reg = rd | ((word & 1) << 5);
2614 			op->reg = rd | ((word & 1) << 5);
2628 			op->reg = VSX_REGISTER_XTP(rd);
2633 			op->reg = rd | ((word & 1) << 5);
2640 			op->reg = rd | ((word & 1) << 5);
2646 			op->reg = rd | ((word & 1) << 5);
2653 			op->reg = rd | ((word & 1) << 5);
2659 			op->reg = rd | ((word & 1) << 5);
2667 			op->reg = rd | ((word & 1) << 5);
2676 			op->reg = rd | ((word & 1) << 5);
2685 			op->reg = rd | ((word & 1) << 5);
2692 			op->reg = rd | ((word & 1) << 5);
2700 			op->reg = rd | ((word & 1) << 5);
2707 			op->reg = rd | ((word & 1) << 5);
2715 			op->reg = rd | ((word & 1) << 5);
2724 			op->reg = rd | ((word & 1) << 5);
2733 			op->reg = rd | ((word & 1) << 5);
2740 			op->reg = rd | ((word & 1) << 5);
2748 			op->reg = rd | ((word & 1) << 5);
2852 				break;		/* reg must be even */
2858 			op->reg = rd + 32;
2866 			op->reg = rd + 32;
2897 		op->reg = VSX_REGISTER_XTP(rd);
2922 				op->reg = rd + 32;
2933 			op->reg = rd + 32;
2944 			op->reg = rd + 32;
2955 				op->reg = rd + 32;
2988 		op->reg = rd;
3004 				op->reg = rd + 32;
3010 				op->reg = rd + 32;
3016 				op->reg = rd + 32;
3022 				op->reg = rd + 32;
3028 				op->reg += 32;
3036 				op->reg = rd + 32;
3052 				op->reg = VSX_REGISTER_XTP(rd);
3065 				op->reg = VSX_REGISTER_XTP(rd);
3153 	op->reg = ra;
3161 	op->reg = rd;
3238 			regs->gpr[op->reg] = op->val;
3279 			regs->gpr[op->reg] = regs->xer & 0xffffffffUL;
3282 			regs->gpr[op->reg] = regs->link;
3285 			regs->gpr[op->reg] = regs->ctr;
3364 			err = do_lqarx(ea, &regs->gpr[op->reg]);
3375 			regs->gpr[op->reg] = val;
3401 			err = do_stqcx(ea, regs->gpr[op->reg],
3402 				       regs->gpr[op->reg + 1], &cr);
3419 			err = emulate_lq(regs, ea, op->reg, cross_endian);
3423 		err = read_mem(&regs->gpr[op->reg], ea, size, regs);
3426 				do_signext(&regs->gpr[op->reg], size);
3428 				do_byterev(&regs->gpr[op->reg], size);
3449 		err = do_vec_load(op->reg, ea, size, regs, cross_endian);
3460 		if (op->reg >= 32 && (op->vsx_flags & VSX_CHECK_VEC))
3471 		rd = op->reg;
3485 			/* reg number wraps from 31 to 0 for lsw[ix] */
3493 			err = emulate_stq(regs, ea, op->reg, cross_endian);
3498 		    op->reg == 1 && op->update_reg == 1 &&
3520 		err = do_vec_store(op->reg, ea, size, regs, cross_endian);
3531 		if (op->reg >= 32 && (op->vsx_flags & VSX_CHECK_VEC))
3542 		rd = op->reg;
3555 			/* reg number wraps from 31 to 0 for stsw[ix] */
3619 			if (op.reg == 0)
3623 			if (op.reg == 0)
3640 		regs->gpr[op.reg] = regs->msr & MSR_MASK;
3644 		val = regs->gpr[op.reg];