Lines Matching refs:op
85 struct instruction_op *op)
92 op->type |= DECCTR;
575 static int do_fp_load(struct instruction_op *op, unsigned long ea,
588 nb = GETSIZE(op->type);
593 rn = op->reg;
604 if (op->type & FPCONV)
606 else if (op->type & SIGNEXT)
628 static int do_fp_store(struct instruction_op *op, unsigned long ea,
640 nb = GETSIZE(op->type);
645 rn = op->reg;
652 if (op->type & FPCONV)
783 void emulate_vsx_load(struct instruction_op *op, union vsx_reg *reg,
792 size = GETSIZE(op->type);
795 switch (op->element_size) {
803 if (IS_LE && (op->vsx_flags & VSX_LDLEFT))
816 if (op->type & SIGNEXT) {
819 } else if (op->vsx_flags & VSX_FPCONV) {
829 } else if (op->vsx_flags & VSX_SPLAT)
840 if (op->vsx_flags & VSX_SPLAT) {
869 void emulate_vsx_store(struct instruction_op *op, const union vsx_reg *reg,
879 size = GETSIZE(op->type);
881 switch (op->element_size) {
902 if (IS_LE && (op->vsx_flags & VSX_LDLEFT))
916 if (size < 8 && op->vsx_flags & VSX_FPCONV) {
961 static nokprobe_inline int do_vsx_load(struct instruction_op *op,
965 int reg = op->reg;
969 int size = GETSIZE(op->type);
975 emulate_vsx_load(op, buf, mem, cross_endian);
1008 static nokprobe_inline int do_vsx_store(struct instruction_op *op,
1012 int reg = op->reg;
1016 int size = GETSIZE(op->type);
1051 emulate_vsx_store(op, buf, mem, cross_endian);
1097 #define __put_user_asmx(x, addr, err, op, cr) \
1101 "1: " op " %2,0,%3\n" \
1113 #define __get_user_asmx(x, addr, err, op) \
1117 "1: "op" %1,0,%2\n" \
1128 #define __cacheop_user_asmx(addr, err, op) \
1130 "1: "op" 0,%1\n" \
1141 struct instruction_op *op)
1143 long val = op->val;
1145 op->type |= SETCC;
1146 op->ccval = (regs->ccr & 0x0fffffff) | ((regs->xer >> 3) & 0x10000000);
1150 op->ccval |= 0x80000000;
1152 op->ccval |= 0x40000000;
1154 op->ccval |= 0x20000000;
1157 static nokprobe_inline void set_ca32(struct instruction_op *op, bool val)
1161 op->xerval |= XER_CA32;
1163 op->xerval &= ~XER_CA32;
1168 struct instruction_op *op, int rd,
1176 op->type = COMPUTE | SETREG | SETXER;
1177 op->reg = rd;
1178 op->val = val;
1181 op->xerval = regs->xer;
1183 op->xerval |= XER_CA;
1185 op->xerval &= ~XER_CA;
1187 set_ca32(op, (unsigned int)val < (unsigned int)val1 ||
1192 struct instruction_op *op,
1197 op->type = COMPUTE | SETCC;
1206 op->ccval = (regs->ccr & ~(0xf << shift)) | (crval << shift);
1210 struct instruction_op *op,
1216 op->type = COMPUTE | SETCC;
1225 op->ccval = (regs->ccr & ~(0xf << shift)) | (crval << shift);
1229 struct instruction_op *op,
1241 op->val = out_val;
1249 struct instruction_op *op,
1260 op->val = out;
1266 op->val = out & 0x0000003f0000003fULL;
1271 op->val = out; /* popcntd */
1276 struct instruction_op *op,
1289 op->val = perm;
1297 struct instruction_op *op,
1304 op->val = res & 0x0000000100000001ULL;
1309 op->val = res & 1; /*prtyd */
1345 * Decode an instruction, and return information about it in *op
1348 * instructions can be emulated just using the information in *op.
1351 * updating *regs with the information in *op, -1 if we need the
1355 int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
1371 op->type = COMPUTE;
1376 op->type = BRANCH;
1380 op->val = truncate_if_32bit(regs->msr, imm);
1382 op->type |= SETLK;
1383 if (branch_taken(word, regs, op))
1384 op->type |= BRTAKEN;
1388 op->type = SYSCALL;
1391 op->type = SYSCALL_VECTORED_0;
1395 op->type = UNKNOWN;
1398 op->type = BRANCH | BRTAKEN;
1404 op->val = truncate_if_32bit(regs->msr, imm);
1406 op->type |= SETLK;
1411 op->type = COMPUTE + SETCC;
1417 op->ccval = (regs->ccr & ~(0xfUL << rd)) | (val << rd);
1422 op->type = BRANCH;
1424 op->val = truncate_if_32bit(regs->msr, imm);
1426 op->type |= SETLK;
1427 if (branch_taken(word, regs, op))
1428 op->type |= BRTAKEN;
1434 op->type = RFI;
1438 op->type = BARRIER | BARRIER_ISYNC;
1449 op->type = COMPUTE + SETCC;
1456 op->ccval = (regs->ccr & ~(1UL << (31 - rd))) |
1464 op->type = BARRIER + BARRIER_SYNC;
1468 op->type = BARRIER + BARRIER_LWSYNC;
1471 op->type = BARRIER + BARRIER_PTESYNC;
1478 op->type = BARRIER + BARRIER_EIEIO;
1498 op->reg = rd;
1499 op->val = regs->gpr[rd];
1508 op->type = COMPUTE | PREFIXED;
1509 op->val = mlsd_8lsd_ea(word, suffix, regs);
1537 "=r" (op->val) : "r" (regs->gpr[ra]),
1543 "=r" (op->val) : "r" (regs->gpr[ra]),
1549 "=r" (op->val) : "r" (regs->gpr[ra]),
1562 op->val = regs->gpr[ra] * (short) word;
1567 add_with_carry(regs, op, rd, ~regs->gpr[ra], imm, 1);
1577 do_cmp_unsigned(regs, op, val, imm, rd >> 2);
1587 do_cmp_signed(regs, op, val, imm, rd >> 2);
1592 add_with_carry(regs, op, rd, regs->gpr[ra], imm, 0);
1597 add_with_carry(regs, op, rd, regs->gpr[ra], imm, 0);
1598 set_cr0(regs, op);
1605 op->val = imm;
1612 op->val = imm;
1622 op->val = regs->nip + (imm << 16) + 4;
1625 op->type = UNKNOWN;
1633 op->val = (regs->gpr[ra] & ~imm) | (ROTATE(val, rb) & imm);
1640 op->val = ROTATE(val, rb) & MASK32(mb, me);
1648 op->val = ROTATE(val, rb) & MASK32(mb, me);
1652 op->val = regs->gpr[rd] | (unsigned short) word;
1657 op->val = regs->gpr[rd] | (imm << 16);
1661 op->val = regs->gpr[rd] ^ (unsigned short) word;
1666 op->val = regs->gpr[rd] ^ (imm << 16);
1670 op->val = regs->gpr[rd] & (unsigned short) word;
1671 set_cr0(regs, op);
1676 op->val = regs->gpr[rd] & (imm << 16);
1677 set_cr0(regs, op);
1702 op->val = val;
1709 op->val = val & MASK64_L(mb);
1712 op->val = val & MASK64_R(mb);
1717 op->type = UNKNOWN; /* illegal instruction */
1727 op->val = (val) ? val2 : regs->gpr[rb];
1747 op->type = MFMSR;
1748 op->reg = rd;
1753 op->type = MTMSR;
1754 op->reg = rd;
1755 op->val = 0xffffffff & ~(MSR_ME | MSR_LE);
1761 op->type = MTMSR;
1762 op->reg = rd;
1766 op->val = imm;
1780 op->val = regs->ccr & imm;
1797 op->val = -1;
1800 op->val = 1;
1802 op->val = 0;
1806 op->type = COMPUTE + SETCC;
1809 op->ccval = regs->ccr;
1812 op->ccval = (op->ccval & ~imm) |
1820 op->type = MFSPR;
1821 op->reg = rd;
1822 op->spr = spr;
1830 op->type = MTSPR;
1831 op->val = regs->gpr[rd];
1832 op->spr = spr;
1851 do_cmp_signed(regs, op, val, val2, rd >> 2);
1864 do_cmp_unsigned(regs, op, val, val2, rd >> 2);
1868 do_cmpb(regs, op, regs->gpr[rd], regs->gpr[rb]);
1875 add_with_carry(regs, op, rd, ~regs->gpr[ra],
1880 asm("mulhdu %0,%1,%2" : "=r" (op->val) :
1885 add_with_carry(regs, op, rd, regs->gpr[ra],
1890 asm("mulhwu %0,%1,%2" : "=r" (op->val) :
1895 op->val = regs->gpr[rb] - regs->gpr[ra];
1899 asm("mulhd %0,%1,%2" : "=r" (op->val) :
1904 asm("mulhw %0,%1,%2" : "=r" (op->val) :
1909 op->val = -regs->gpr[ra];
1913 add_with_carry(regs, op, rd, ~regs->gpr[ra],
1918 add_with_carry(regs, op, rd, regs->gpr[ra],
1923 add_with_carry(regs, op, rd, ~regs->gpr[ra], 0L,
1928 add_with_carry(regs, op, rd, regs->gpr[ra], 0L,
1933 add_with_carry(regs, op, rd, ~regs->gpr[ra], -1L,
1938 op->val = regs->gpr[ra] * regs->gpr[rb];
1942 add_with_carry(regs, op, rd, regs->gpr[ra], -1L,
1947 op->val = (long)(int) regs->gpr[ra] *
1955 op->val = regs->gpr[ra] % regs->gpr[rb];
1959 op->val = regs->gpr[ra] + regs->gpr[rb];
1965 op->val = (unsigned int) regs->gpr[ra] %
1970 op->val = regs->gpr[ra] / regs->gpr[rb];
1974 op->val = (unsigned int) regs->gpr[ra] /
1979 op->val = (long int) regs->gpr[ra] /
1984 op->val = (int) regs->gpr[ra] /
1990 "=r" (op->val) : "r" (regs->gpr[ra]),
1995 "=r" (op->val) : "r" (regs->gpr[ra]),
2005 asm volatile(PPC_DARN(%0, 0) : "=r" (op->val));
2010 asm volatile(PPC_DARN(%0, 1) : "=r" (op->val));
2015 asm volatile(PPC_DARN(%0, 2) : "=r" (op->val));
2024 op->val = (long int) regs->gpr[ra] %
2031 op->val = (int) regs->gpr[ra] %
2041 op->val = ( val ? __builtin_clz(val) : 32 );
2046 op->val = ( val ? __builtin_clzl(val) : 64 );
2050 op->val = regs->gpr[rd] & regs->gpr[rb];
2054 op->val = regs->gpr[rd] & ~regs->gpr[rb];
2058 do_popcnt(regs, op, regs->gpr[rd], 8);
2062 op->val = ~(regs->gpr[rd] | regs->gpr[rb]);
2066 do_prty(regs, op, regs->gpr[rd], 32);
2070 do_prty(regs, op, regs->gpr[rd], 64);
2074 do_bpermd(regs, op, regs->gpr[rd], regs->gpr[rb]);
2078 op->val = ~(regs->gpr[rd] ^ regs->gpr[rb]);
2082 op->val = regs->gpr[rd] ^ regs->gpr[rb];
2086 do_popcnt(regs, op, regs->gpr[rd], 32);
2090 op->val = regs->gpr[rd] | ~regs->gpr[rb];
2094 op->val = regs->gpr[rd] | regs->gpr[rb];
2098 op->val = ~(regs->gpr[rd] & regs->gpr[rb]);
2102 do_popcnt(regs, op, regs->gpr[rd], 64);
2109 op->val = (val ? __builtin_ctz(val) : 32);
2116 op->val = (val ? __builtin_ctzl(val) : 64);
2120 op->val = (signed short) regs->gpr[rd];
2124 op->val = (signed char) regs->gpr[rd];
2128 op->val = (signed int) regs->gpr[rd];
2138 op->val = (regs->gpr[rd] << sh) & 0xffffffffUL;
2140 op->val = 0;
2146 op->val = (regs->gpr[rd] & 0xffffffffUL) >> sh;
2148 op->val = 0;
2152 op->type = COMPUTE + SETREG + SETXER;
2155 op->val = ival >> (sh < 32 ? sh : 31);
2156 op->xerval = regs->xer;
2158 op->xerval |= XER_CA;
2160 op->xerval &= ~XER_CA;
2161 set_ca32(op, op->xerval & XER_CA);
2165 op->type = COMPUTE + SETREG + SETXER;
2168 op->val = ival >> sh;
2169 op->xerval = regs->xer;
2171 op->xerval |= XER_CA;
2173 op->xerval &= ~XER_CA;
2174 set_ca32(op, op->xerval & XER_CA);
2181 op->val = regs->gpr[rd] << sh;
2183 op->val = 0;
2189 op->val = regs->gpr[rd] >> sh;
2191 op->val = 0;
2195 op->type = COMPUTE + SETREG + SETXER;
2198 op->val = ival >> (sh < 64 ? sh : 63);
2199 op->xerval = regs->xer;
2201 op->xerval |= XER_CA;
2203 op->xerval &= ~XER_CA;
2204 set_ca32(op, op->xerval & XER_CA);
2209 op->type = COMPUTE + SETREG + SETXER;
2212 op->val = ival >> sh;
2213 op->xerval = regs->xer;
2215 op->xerval |= XER_CA;
2217 op->xerval &= ~XER_CA;
2218 set_ca32(op, op->xerval & XER_CA);
2225 op->type = COMPUTE + SETREG;
2229 op->val = ROTATE(val, sh) & MASK64(0, 63 - sh);
2231 op->val = val;
2240 op->type = MKOP(CACHEOP, DCBST, 0);
2241 op->ea = xform_ea(word, regs);
2245 op->type = MKOP(CACHEOP, DCBF, 0);
2246 op->ea = xform_ea(word, regs);
2250 op->type = MKOP(CACHEOP, DCBTST, 0);
2251 op->ea = xform_ea(word, regs);
2252 op->reg = rd;
2256 op->type = MKOP(CACHEOP, DCBTST, 0);
2257 op->ea = xform_ea(word, regs);
2258 op->reg = rd;
2262 op->type = MKOP(CACHEOP, ICBI, 0);
2263 op->ea = xform_ea(word, regs);
2267 op->type = MKOP(CACHEOP, DCBZ, 0);
2268 op->ea = xform_ea(word, regs);
2277 op->type = UNKNOWN;
2278 op->update_reg = ra;
2279 op->reg = rd;
2280 op->val = regs->gpr[rd];
2282 op->vsx_flags = 0;
2287 op->ea = xform_ea(word, regs);
2290 op->type = MKOP(LARX, 0, 4);
2294 op->type = MKOP(STCX, 0, 4);
2299 op->type = MKOP(LARX, 0, 1);
2303 op->type = MKOP(STCX, 0, 1);
2307 op->type = MKOP(LARX, 0, 2);
2311 op->type = MKOP(STCX, 0, 2);
2316 op->type = MKOP(LARX, 0, 8);
2320 op->type = MKOP(STCX, 0, 8);
2325 op->type = MKOP(LARX, 0, 16);
2330 op->type = MKOP(STCX, 0, 16);
2336 op->type = MKOP(LOAD, u, 4);
2341 op->type = MKOP(LOAD, u, 1);
2350 op->type = MKOP(LOAD_VMX, 0, 1);
2351 op->element_size = 1;
2355 op->type = MKOP(LOAD_VMX, 0, 2);
2356 op->element_size = 2;
2360 op->type = MKOP(LOAD_VMX, 0, 4);
2361 op->element_size = 4;
2366 op->type = MKOP(LOAD_VMX, 0, 16);
2367 op->element_size = 16;
2371 op->type = MKOP(STORE_VMX, 0, 1);
2372 op->element_size = 1;
2376 op->type = MKOP(STORE_VMX, 0, 2);
2377 op->element_size = 2;
2381 op->type = MKOP(STORE_VMX, 0, 4);
2382 op->element_size = 4;
2387 op->type = MKOP(STORE_VMX, 0, 16);
2394 op->type = MKOP(LOAD, u, 8);
2399 op->type = MKOP(STORE, u, 8);
2405 op->type = MKOP(STORE, u, 4);
2410 op->type = MKOP(STORE, u, 1);
2415 op->type = MKOP(LOAD, u, 2);
2421 op->type = MKOP(LOAD, SIGNEXT | u, 4);
2427 op->type = MKOP(LOAD, SIGNEXT | u, 2);
2432 op->type = MKOP(STORE, u, 2);
2437 op->type = MKOP(LOAD, BYTEREV, 8);
2442 op->type = MKOP(LOAD_MULTI, 0, regs->xer & 0x7f);
2446 op->type = MKOP(LOAD, BYTEREV, 4);
2452 op->type = MKOP(LOAD_MULTI, 0, rb);
2453 op->ea = ra ? regs->gpr[ra] : 0;
2459 op->type = MKOP(LOAD_FP, u | FPCONV, 4);
2464 op->type = MKOP(LOAD_FP, u, 8);
2469 op->type = MKOP(STORE_FP, u | FPCONV, 4);
2474 op->type = MKOP(STORE_FP, u, 8);
2479 op->type = MKOP(LOAD_FP, 0, 16);
2483 op->type = MKOP(LOAD_FP, SIGNEXT, 4);
2487 op->type = MKOP(LOAD_FP, 0, 4);
2491 op->type = MKOP(STORE_FP, 0, 16);
2495 op->type = MKOP(STORE_FP, 0, 4);
2502 op->type = MKOP(STORE, BYTEREV, 8);
2503 op->val = byterev_8(regs->gpr[rd]);
2508 op->type = MKOP(STORE_MULTI, 0, regs->xer & 0x7f);
2512 op->type = MKOP(STORE, BYTEREV, 4);
2513 op->val = byterev_4(regs->gpr[rd]);
2519 op->type = MKOP(STORE_MULTI, 0, rb);
2520 op->ea = ra ? regs->gpr[ra] : 0;
2524 op->type = MKOP(LOAD, BYTEREV, 2);
2528 op->type = MKOP(STORE, BYTEREV, 2);
2529 op->val = byterev_2(regs->gpr[rd]);
2534 op->reg = rd | ((word & 1) << 5);
2535 op->type = MKOP(LOAD_VSX, 0, 4);
2536 op->element_size = 8;
2540 op->reg = rd | ((word & 1) << 5);
2541 op->type = MKOP(LOAD_VSX, SIGNEXT, 4);
2542 op->element_size = 8;
2546 op->reg = rd | ((word & 1) << 5);
2547 op->type = MKOP(STORE_VSX, 0, 4);
2548 op->element_size = 8;
2554 op->reg = rd | ((word & 1) << 5);
2555 op->type = MKOP(LOAD_VSX, 0, 16);
2556 op->element_size = 16;
2557 op->vsx_flags = VSX_CHECK_VEC;
2565 op->reg = rd | ((word & 1) << 5);
2566 op->ea = ra ? regs->gpr[ra] : 0;
2570 op->type = MKOP(LOAD_VSX, 0, nb);
2571 op->element_size = 16;
2572 op->vsx_flags = ((word & 0x20) ? VSX_LDLEFT : 0) |
2577 op->reg = rd | ((word & 1) << 5);
2578 op->type = MKOP(LOAD_VSX, 0, 8);
2579 op->element_size = 8;
2580 op->vsx_flags = VSX_SPLAT;
2586 op->reg = VSX_REGISTER_XTP(rd);
2587 op->type = MKOP(LOAD_VSX, 0, 32);
2588 op->element_size = 32;
2594 op->reg = rd | ((word & 1) << 5);
2595 op->type = MKOP(LOAD_VSX, 0, 4);
2596 op->element_size = 4;
2597 op->vsx_flags = VSX_SPLAT | VSX_CHECK_VEC;
2603 op->reg = rd | ((word & 1) << 5);
2604 op->type = MKOP(STORE_VSX, 0, 16);
2605 op->element_size = 16;
2606 op->vsx_flags = VSX_CHECK_VEC;
2614 op->reg = rd | ((word & 1) << 5);
2615 op->ea = ra ? regs->gpr[ra] : 0;
2619 op->type = MKOP(STORE_VSX, 0, nb);
2620 op->element_size = 16;
2621 op->vsx_flags = ((word & 0x20) ? VSX_LDLEFT : 0) |
2628 op->reg = VSX_REGISTER_XTP(rd);
2629 op->type = MKOP(STORE_VSX, 0, 32);
2630 op->element_size = 32;
2633 op->reg = rd | ((word & 1) << 5);
2634 op->type = MKOP(LOAD_VSX, 0, 4);
2635 op->element_size = 8;
2636 op->vsx_flags = VSX_FPCONV;
2640 op->reg = rd | ((word & 1) << 5);
2641 op->type = MKOP(LOAD_VSX, 0, 8);
2642 op->element_size = 8;
2646 op->reg = rd | ((word & 1) << 5);
2647 op->type = MKOP(STORE_VSX, 0, 4);
2648 op->element_size = 8;
2649 op->vsx_flags = VSX_FPCONV;
2653 op->reg = rd | ((word & 1) << 5);
2654 op->type = MKOP(STORE_VSX, 0, 8);
2655 op->element_size = 8;
2659 op->reg = rd | ((word & 1) << 5);
2660 op->type = MKOP(LOAD_VSX, 0, 16);
2661 op->element_size = 4;
2667 op->reg = rd | ((word & 1) << 5);
2668 op->type = MKOP(LOAD_VSX, 0, 1);
2669 op->element_size = 8;
2670 op->vsx_flags = VSX_CHECK_VEC;
2676 op->reg = rd | ((word & 1) << 5);
2677 op->type = MKOP(LOAD_VSX, 0, 16);
2678 op->element_size = 2;
2679 op->vsx_flags = VSX_CHECK_VEC;
2685 op->reg = rd | ((word & 1) << 5);
2686 op->type = MKOP(LOAD_VSX, 0, 2);
2687 op->element_size = 8;
2688 op->vsx_flags = VSX_CHECK_VEC;
2692 op->reg = rd | ((word & 1) << 5);
2693 op->type = MKOP(LOAD_VSX, 0, 16);
2694 op->element_size = 8;
2700 op->reg = rd | ((word & 1) << 5);
2701 op->type = MKOP(LOAD_VSX, 0, 16);
2702 op->element_size = 1;
2703 op->vsx_flags = VSX_CHECK_VEC;
2707 op->reg = rd | ((word & 1) << 5);
2708 op->type = MKOP(STORE_VSX, 0, 16);
2709 op->element_size = 4;
2715 op->reg = rd | ((word & 1) << 5);
2716 op->type = MKOP(STORE_VSX, 0, 1);
2717 op->element_size = 8;
2718 op->vsx_flags = VSX_CHECK_VEC;
2724 op->reg = rd | ((word & 1) << 5);
2725 op->type = MKOP(STORE_VSX, 0, 16);
2726 op->element_size = 2;
2727 op->vsx_flags = VSX_CHECK_VEC;
2733 op->reg = rd | ((word & 1) << 5);
2734 op->type = MKOP(STORE_VSX, 0, 2);
2735 op->element_size = 8;
2736 op->vsx_flags = VSX_CHECK_VEC;
2740 op->reg = rd | ((word & 1) << 5);
2741 op->type = MKOP(STORE_VSX, 0, 16);
2742 op->element_size = 8;
2748 op->reg = rd | ((word & 1) << 5);
2749 op->type = MKOP(STORE_VSX, 0, 16);
2750 op->element_size = 1;
2751 op->vsx_flags = VSX_CHECK_VEC;
2760 op->type = MKOP(LOAD, u, 4);
2761 op->ea = dform_ea(word, regs);
2766 op->type = MKOP(LOAD, u, 1);
2767 op->ea = dform_ea(word, regs);
2772 op->type = MKOP(STORE, u, 4);
2773 op->ea = dform_ea(word, regs);
2778 op->type = MKOP(STORE, u, 1);
2779 op->ea = dform_ea(word, regs);
2784 op->type = MKOP(LOAD, u, 2);
2785 op->ea = dform_ea(word, regs);
2790 op->type = MKOP(LOAD, SIGNEXT | u, 2);
2791 op->ea = dform_ea(word, regs);
2796 op->type = MKOP(STORE, u, 2);
2797 op->ea = dform_ea(word, regs);
2803 op->type = MKOP(LOAD_MULTI, 0, 4 * (32 - rd));
2804 op->ea = dform_ea(word, regs);
2808 op->type = MKOP(STORE_MULTI, 0, 4 * (32 - rd));
2809 op->ea = dform_ea(word, regs);
2815 op->type = MKOP(LOAD_FP, u | FPCONV, 4);
2816 op->ea = dform_ea(word, regs);
2821 op->type = MKOP(LOAD_FP, u, 8);
2822 op->ea = dform_ea(word, regs);
2827 op->type = MKOP(STORE_FP, u | FPCONV, 4);
2828 op->ea = dform_ea(word, regs);
2833 op->type = MKOP(STORE_FP, u, 8);
2834 op->ea = dform_ea(word, regs);
2841 op->type = MKOP(LOAD, 0, 16);
2842 op->ea = dqform_ea(word, regs);
2848 op->ea = dsform_ea(word, regs);
2853 op->type = MKOP(LOAD_FP, 0, 16);
2858 op->reg = rd + 32;
2859 op->type = MKOP(LOAD_VSX, 0, 8);
2860 op->element_size = 8;
2861 op->vsx_flags = VSX_CHECK_VEC;
2866 op->reg = rd + 32;
2867 op->type = MKOP(LOAD_VSX, 0, 4);
2868 op->element_size = 8;
2869 op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC;
2877 op->ea = dsform_ea(word, regs);
2880 op->type = MKOP(LOAD, 0, 8);
2883 op->type = MKOP(LOAD, UPDATE, 8);
2886 op->type = MKOP(LOAD, SIGNEXT, 4);
2896 op->ea = dqform_ea(word, regs);
2897 op->reg = VSX_REGISTER_XTP(rd);
2898 op->element_size = 32;
2901 op->type = MKOP(LOAD_VSX, 0, 32);
2904 op->type = MKOP(STORE_VSX, 0, 32);
2913 op->ea = dsform_ea(word, regs);
2914 op->type = MKOP(STORE_FP, 0, 16);
2920 op->ea = dqform_ea(word, regs);
2922 op->reg = rd + 32;
2923 op->type = MKOP(LOAD_VSX, 0, 16);
2924 op->element_size = 16;
2925 op->vsx_flags = VSX_CHECK_VEC;
2932 op->ea = dsform_ea(word, regs);
2933 op->reg = rd + 32;
2934 op->type = MKOP(STORE_VSX, 0, 8);
2935 op->element_size = 8;
2936 op->vsx_flags = VSX_CHECK_VEC;
2943 op->ea = dsform_ea(word, regs);
2944 op->reg = rd + 32;
2945 op->type = MKOP(STORE_VSX, 0, 4);
2946 op->element_size = 8;
2947 op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC;
2953 op->ea = dqform_ea(word, regs);
2955 op->reg = rd + 32;
2956 op->type = MKOP(STORE_VSX, 0, 16);
2957 op->element_size = 16;
2958 op->vsx_flags = VSX_CHECK_VEC;
2966 op->ea = dsform_ea(word, regs);
2969 op->type = MKOP(STORE, 0, 8);
2972 op->type = MKOP(STORE, UPDATE, 8);
2976 op->type = MKOP(STORE, 0, 16);
2986 op->update_reg = ra;
2988 op->reg = rd;
2989 op->val = regs->gpr[rd];
2997 op->ea = mlsd_8lsd_ea(word, suffix, regs);
3000 op->type = MKOP(LOAD, PREFIXED | SIGNEXT, 4);
3004 op->reg = rd + 32;
3005 op->type = MKOP(LOAD_VSX, PREFIXED, 8);
3006 op->element_size = 8;
3007 op->vsx_flags = VSX_CHECK_VEC;
3010 op->reg = rd + 32;
3011 op->type = MKOP(LOAD_VSX, PREFIXED, 4);
3012 op->element_size = 8;
3013 op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC;
3016 op->reg = rd + 32;
3017 op->type = MKOP(STORE_VSX, PREFIXED, 8);
3018 op->element_size = 8;
3019 op->vsx_flags = VSX_CHECK_VEC;
3022 op->reg = rd + 32;
3023 op->type = MKOP(STORE_VSX, PREFIXED, 4);
3024 op->element_size = 8;
3025 op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC;
3028 op->reg += 32;
3031 op->type = MKOP(LOAD_VSX, PREFIXED, 16);
3032 op->element_size = 16;
3033 op->vsx_flags = VSX_CHECK_VEC;
3036 op->reg = rd + 32;
3039 op->type = MKOP(STORE_VSX, PREFIXED, 16);
3040 op->element_size = 16;
3041 op->vsx_flags = VSX_CHECK_VEC;
3045 op->type = MKOP(LOAD, PREFIXED, 16);
3048 op->type = MKOP(LOAD, PREFIXED, 8);
3052 op->reg = VSX_REGISTER_XTP(rd);
3053 op->type = MKOP(LOAD_VSX, PREFIXED, 32);
3054 op->element_size = 32;
3058 op->type = MKOP(STORE, PREFIXED, 16);
3061 op->type = MKOP(STORE, PREFIXED, 8);
3065 op->reg = VSX_REGISTER_XTP(rd);
3066 op->type = MKOP(STORE_VSX, PREFIXED, 32);
3067 op->element_size = 32;
3077 op->ea = mlsd_8lsd_ea(word, suffix, regs);
3080 op->type = MKOP(LOAD, PREFIXED, 4);
3083 op->type = MKOP(LOAD, PREFIXED, 1);
3086 op->type = MKOP(STORE, PREFIXED, 4);
3089 op->type = MKOP(STORE, PREFIXED, 1);
3092 op->type = MKOP(LOAD, PREFIXED, 2);
3095 op->type = MKOP(LOAD, PREFIXED | SIGNEXT, 2);
3098 op->type = MKOP(STORE, PREFIXED, 2);
3101 op->type = MKOP(LOAD_FP, PREFIXED | FPCONV, 4);
3104 op->type = MKOP(LOAD_FP, PREFIXED, 8);
3107 op->type = MKOP(STORE_FP, PREFIXED | FPCONV, 4);
3110 op->type = MKOP(STORE_FP, PREFIXED, 8);
3121 if (OP_IS_LOAD_STORE(op->type) && (op->type & UPDATE)) {
3122 switch (GETTYPE(op->type)) {
3136 if ((GETTYPE(op->type) == LOAD_VSX ||
3137 GETTYPE(op->type) == STORE_VSX) &&
3146 op->type = UNKNOWN;
3151 set_cr0(regs, op);
3153 op->reg = ra;
3154 op->type |= SETREG;
3159 set_cr0(regs, op);
3161 op->reg = rd;
3162 op->type |= SETREG;
3166 op->type = INTERRUPT | 0x700;
3167 op->val = SRR1_PROGPRIV;
3171 op->type = INTERRUPT | 0x700;
3172 op->val = SRR1_PROGTRAP;
3230 void emulate_update_regs(struct pt_regs *regs, struct instruction_op *op)
3234 next_pc = truncate_if_32bit(regs->msr, regs->nip + GETLENGTH(op->type));
3235 switch (GETTYPE(op->type)) {
3237 if (op->type & SETREG)
3238 regs->gpr[op->reg] = op->val;
3239 if (op->type & SETCC)
3240 regs->ccr = op->ccval;
3241 if (op->type & SETXER)
3242 regs->xer = op->xerval;
3246 if (op->type & SETLK)
3248 if (op->type & BRTAKEN)
3249 next_pc = op->val;
3250 if (op->type & DECCTR)
3255 switch (op->type & BARRIER_MASK) {
3277 switch (op->spr) {
3279 regs->gpr[op->reg] = regs->xer & 0xffffffffUL;
3282 regs->gpr[op->reg] = regs->link;
3285 regs->gpr[op->reg] = regs->ctr;
3293 switch (op->spr) {
3295 regs->xer = op->val & 0xffffffffUL;
3298 regs->link = op->val;
3301 regs->ctr = op->val;
3322 * -EINVAL = unknown operation in *op
3324 int emulate_loadstore(struct pt_regs *regs, struct instruction_op *op)
3334 size = GETSIZE(op->type);
3335 type = GETTYPE(op->type);
3337 ea = truncate_if_32bit(regs->msr, op->ea);
3364 err = do_lqarx(ea, ®s->gpr[op->reg]);
3375 regs->gpr[op->reg] = val;
3387 __put_user_asmx(op->val, ea, err, "stbcx.", cr);
3390 __put_user_asmx(op->val, ea, err, "sthcx.", cr);
3394 __put_user_asmx(op->val, ea, err, "stwcx.", cr);
3398 __put_user_asmx(op->val, ea, err, "stdcx.", cr);
3401 err = do_stqcx(ea, regs->gpr[op->reg],
3402 regs->gpr[op->reg + 1], &cr);
3419 err = emulate_lq(regs, ea, op->reg, cross_endian);
3423 err = read_mem(®s->gpr[op->reg], ea, size, regs);
3425 if (op->type & SIGNEXT)
3426 do_signext(®s->gpr[op->reg], size);
3427 if ((op->type & BYTEREV) == (cross_endian ? 0 : BYTEREV))
3428 do_byterev(®s->gpr[op->reg], size);
3442 err = do_fp_load(op, ea, regs, cross_endian);
3449 err = do_vec_load(op->reg, ea, size, regs, cross_endian);
3460 if (op->reg >= 32 && (op->vsx_flags & VSX_CHECK_VEC))
3464 err = do_vsx_load(op, ea, regs, cross_endian);
3471 rd = op->reg;
3493 err = emulate_stq(regs, ea, op->reg, cross_endian);
3497 if ((op->type & UPDATE) && size == sizeof(long) &&
3498 op->reg == 1 && op->update_reg == 1 &&
3505 do_byterev(&op->val, size);
3506 err = write_mem(op->val, ea, size, regs);
3513 err = do_fp_store(op, ea, regs, cross_endian);
3520 err = do_vec_store(op->reg, ea, size, regs, cross_endian);
3531 if (op->reg >= 32 && (op->vsx_flags & VSX_CHECK_VEC))
3535 err = do_vsx_store(op, ea, regs, cross_endian);
3542 rd = op->reg;
3567 if (op->type & UPDATE)
3568 regs->gpr[op->update_reg] = op->ea;
3583 struct instruction_op op;
3588 r = analyse_instr(&op, regs, instr);
3592 emulate_update_regs(regs, &op);
3597 type = GETTYPE(op.type);
3600 err = emulate_loadstore(regs, &op);
3608 ea = truncate_if_32bit(regs->msr, op.ea);
3611 switch (op.type & CACHEOP_MASK) {
3619 if (op.reg == 0)
3623 if (op.reg == 0)
3640 regs->gpr[op.reg] = regs->msr & MSR_MASK;
3644 val = regs->gpr[op.reg];
3648 /* here op.val is the mask of bits to change */
3649 regs_set_return_msr(regs, (regs->msr & ~op.val) | (val & op.val));
3673 truncate_if_32bit(regs->msr, regs->nip + GETLENGTH(op.type)));