Lines Matching defs:val
125 u32 val, int idx);
129 uint32_t val);
580 uint32_t val)
594 src->idr = val & mask;
625 uint32_t val)
630 src->output = val & ILR_INTTGT_MASK;
639 uint32_t val)
651 (opp->src[n_IRQ].ivpr & IVPR_ACTIVITY_MASK) | (val & mask);
673 pr_debug("Set IVPR %d to 0x%08x -> 0x%08x\n", n_IRQ, val,
677 static void openpic_gcr_write(struct openpic *opp, uint64_t val)
679 if (val & GCR_RESET) {
685 opp->gcr |= val & opp->mpic_mode_mask;
688 static int openpic_gbl_write(void *opaque, gpa_t addr, u32 val)
693 pr_debug("%s: addr %#llx <= %08x\n", __func__, addr, val);
708 err = openpic_cpu_write_internal(opp, addr, val,
714 openpic_gcr_write(opp, val);
731 write_IRQreg_ivpr(opp, opp->irq_ipi0 + idx, val);
735 opp->spve = val & opp->vector_mask;
806 static int openpic_tmr_write(void *opaque, gpa_t addr, u32 val)
813 pr_debug("%s: addr %#llx <= %08x\n", __func__, addr, val);
819 opp->tfrr = val;
831 (val & TBCR_CI) == 0 &&
835 opp->timers[idx].tbcr = val;
838 write_IRQreg_ivpr(opp, opp->irq_tim0 + idx, val);
841 write_IRQreg_idr(opp, opp->irq_tim0 + idx, val);
886 static int openpic_src_write(void *opaque, gpa_t addr, u32 val)
891 pr_debug("%s: addr %#llx <= %08x\n", __func__, addr, val);
898 write_IRQreg_ivpr(opp, idx, val);
901 write_IRQreg_idr(opp, idx, val);
904 write_IRQreg_ilr(opp, idx, val);
940 static int openpic_msi_write(void *opaque, gpa_t addr, u32 val)
946 pr_debug("%s: addr %#llx <= 0x%08x\n", __func__, addr, val);
952 srs = val >> MSIIR_SRS_SHIFT;
954 ibs = (val & MSIIR_IBS_MASK) >> MSIIR_IBS_SHIFT;
1015 static int openpic_summary_write(void *opaque, gpa_t addr, u32 val)
1017 pr_debug("%s: addr %#llx <= 0x%08x\n", __func__, addr, val);
1024 u32 val, int idx)
1032 addr, val);
1049 opp->src[opp->irq_ipi0 + idx].destmask |= val;
1054 dst->ctpr = val & 0x0000000F;
1118 static int openpic_cpu_write(void *opaque, gpa_t addr, u32 val)
1122 return openpic_cpu_write_internal(opp, addr, val,
1241 int (*write)(void *opaque, gpa_t addr, u32 val);
1355 static int kvm_mpic_write_internal(struct openpic *opp, gpa_t addr, u32 val)
1365 return mr->write(opp, addr - mr->start_addr, val);
1378 u32 val;
1389 ret = kvm_mpic_read_internal(opp, addr - opp->reg_base, &u.val);
1398 *(u32 *)ptr = u.val;
1399 pr_debug("%s: addr %llx ret %d len 4 val %x\n",
1400 __func__, addr, ret, u.val);
1403 pr_debug("%s: addr %llx ret %d len 1 val %x\n",
1434 pr_debug("%s: addr %llx ret %d val %x\n",
1496 static int access_reg(struct openpic *opp, gpa_t addr, u32 *val, int type)
1506 ret = kvm_mpic_write_internal(opp, addr, *val);
1508 ret = kvm_mpic_read_internal(opp, addr, val);
1512 pr_debug("%s: type %d addr %llx val %x\n", __func__, type, addr, *val);