Lines Matching refs:vcpu
24 static void kvmppc_emul_rfi(struct kvm_vcpu *vcpu)
26 vcpu->arch.regs.nip = vcpu->arch.shared->srr0;
27 kvmppc_set_msr(vcpu, vcpu->arch.shared->srr1);
30 static void kvmppc_emul_rfdi(struct kvm_vcpu *vcpu)
32 vcpu->arch.regs.nip = vcpu->arch.dsrr0;
33 kvmppc_set_msr(vcpu, vcpu->arch.dsrr1);
36 static void kvmppc_emul_rfci(struct kvm_vcpu *vcpu)
38 vcpu->arch.regs.nip = vcpu->arch.csrr0;
39 kvmppc_set_msr(vcpu, vcpu->arch.csrr1);
42 int kvmppc_booke_emulate_op(struct kvm_vcpu *vcpu,
53 kvmppc_emul_rfi(vcpu);
54 kvmppc_set_exit_type(vcpu, EMULATED_RFI_EXITS);
59 kvmppc_emul_rfci(vcpu);
60 kvmppc_set_exit_type(vcpu, EMULATED_RFCI_EXITS);
65 kvmppc_emul_rfdi(vcpu);
66 kvmppc_set_exit_type(vcpu, EMULATED_RFDI_EXITS);
80 kvmppc_set_gpr(vcpu, rt, vcpu->arch.shared->msr);
81 kvmppc_set_exit_type(vcpu, EMULATED_MFMSR_EXITS);
85 kvmppc_set_exit_type(vcpu, EMULATED_MTMSR_EXITS);
86 kvmppc_set_msr(vcpu, kvmppc_get_gpr(vcpu, rs));
90 vcpu->arch.shared->msr = (vcpu->arch.shared->msr & ~MSR_EE)
91 | (kvmppc_get_gpr(vcpu, rs) & MSR_EE);
92 kvmppc_set_exit_type(vcpu, EMULATED_WRTEE_EXITS);
96 vcpu->arch.shared->msr = (vcpu->arch.shared->msr & ~MSR_EE)
98 kvmppc_set_exit_type(vcpu, EMULATED_WRTEE_EXITS);
120 int kvmppc_booke_emulate_mtspr(struct kvm_vcpu *vcpu, int sprn, ulong spr_val)
127 vcpu->arch.shared->dar = spr_val;
130 vcpu->arch.shared->esr = spr_val;
133 vcpu->arch.csrr0 = spr_val;
136 vcpu->arch.csrr1 = spr_val;
139 vcpu->arch.dsrr0 = spr_val;
142 vcpu->arch.dsrr1 = spr_val;
149 if (vcpu->guest_debug)
153 vcpu->arch.dbg_reg.iac1 = spr_val;
160 if (vcpu->guest_debug)
164 vcpu->arch.dbg_reg.iac2 = spr_val;
172 if (vcpu->guest_debug)
176 vcpu->arch.dbg_reg.iac3 = spr_val;
183 if (vcpu->guest_debug)
187 vcpu->arch.dbg_reg.iac4 = spr_val;
195 if (vcpu->guest_debug)
199 vcpu->arch.dbg_reg.dac1 = spr_val;
206 if (vcpu->guest_debug)
210 vcpu->arch.dbg_reg.dac2 = spr_val;
217 if (vcpu->guest_debug)
225 vcpu->arch.dbg_reg.dbcr0 = spr_val;
232 if (vcpu->guest_debug)
236 vcpu->arch.dbg_reg.dbcr1 = spr_val;
243 if (vcpu->guest_debug)
247 vcpu->arch.dbg_reg.dbcr2 = spr_val;
254 if (vcpu->guest_debug)
257 vcpu->arch.dbsr &= ~spr_val;
258 if (!(vcpu->arch.dbsr & ~DBSR_IDE))
259 kvmppc_core_dequeue_debug(vcpu);
262 kvmppc_clr_tsr_bits(vcpu, spr_val);
269 if (vcpu->arch.tcr & TCR_WRC_MASK) {
271 spr_val |= vcpu->arch.tcr & TCR_WRC_MASK;
273 kvmppc_set_tcr(vcpu, spr_val);
277 vcpu->arch.decar = spr_val;
285 kvmppc_set_sprg4(vcpu, spr_val);
288 kvmppc_set_sprg5(vcpu, spr_val);
291 kvmppc_set_sprg6(vcpu, spr_val);
294 kvmppc_set_sprg7(vcpu, spr_val);
298 vcpu->arch.ivpr = spr_val;
304 vcpu->arch.ivor[BOOKE_IRQPRIO_CRITICAL] = spr_val;
307 vcpu->arch.ivor[BOOKE_IRQPRIO_MACHINE_CHECK] = spr_val;
310 vcpu->arch.ivor[BOOKE_IRQPRIO_DATA_STORAGE] = spr_val;
316 vcpu->arch.ivor[BOOKE_IRQPRIO_INST_STORAGE] = spr_val;
319 vcpu->arch.ivor[BOOKE_IRQPRIO_EXTERNAL] = spr_val;
322 vcpu->arch.ivor[BOOKE_IRQPRIO_ALIGNMENT] = spr_val;
325 vcpu->arch.ivor[BOOKE_IRQPRIO_PROGRAM] = spr_val;
328 vcpu->arch.ivor[BOOKE_IRQPRIO_FP_UNAVAIL] = spr_val;
331 vcpu->arch.ivor[BOOKE_IRQPRIO_SYSCALL] = spr_val;
337 vcpu->arch.ivor[BOOKE_IRQPRIO_AP_UNAVAIL] = spr_val;
340 vcpu->arch.ivor[BOOKE_IRQPRIO_DECREMENTER] = spr_val;
343 vcpu->arch.ivor[BOOKE_IRQPRIO_FIT] = spr_val;
346 vcpu->arch.ivor[BOOKE_IRQPRIO_WATCHDOG] = spr_val;
349 vcpu->arch.ivor[BOOKE_IRQPRIO_DTLB_MISS] = spr_val;
352 vcpu->arch.ivor[BOOKE_IRQPRIO_ITLB_MISS] = spr_val;
355 vcpu->arch.ivor[BOOKE_IRQPRIO_DEBUG] = spr_val;
358 vcpu->arch.mcsr &= ~spr_val;
362 kvmppc_set_epcr(vcpu, spr_val);
364 mtspr(SPRN_EPCR, vcpu->arch.shadow_epcr);
373 current->thread.debug = vcpu->arch.dbg_reg;
374 switch_booke_debug_regs(&vcpu->arch.dbg_reg);
379 int kvmppc_booke_emulate_mfspr(struct kvm_vcpu *vcpu, int sprn, ulong *spr_val)
385 *spr_val = vcpu->arch.ivpr;
388 *spr_val = vcpu->arch.shared->dar;
391 *spr_val = vcpu->arch.shared->esr;
394 *spr_val = vcpu->arch.epr;
397 *spr_val = vcpu->arch.csrr0;
400 *spr_val = vcpu->arch.csrr1;
403 *spr_val = vcpu->arch.dsrr0;
406 *spr_val = vcpu->arch.dsrr1;
409 *spr_val = vcpu->arch.dbg_reg.iac1;
412 *spr_val = vcpu->arch.dbg_reg.iac2;
416 *spr_val = vcpu->arch.dbg_reg.iac3;
419 *spr_val = vcpu->arch.dbg_reg.iac4;
423 *spr_val = vcpu->arch.dbg_reg.dac1;
426 *spr_val = vcpu->arch.dbg_reg.dac2;
429 *spr_val = vcpu->arch.dbg_reg.dbcr0;
430 if (vcpu->guest_debug)
434 *spr_val = vcpu->arch.dbg_reg.dbcr1;
437 *spr_val = vcpu->arch.dbg_reg.dbcr2;
440 *spr_val = vcpu->arch.dbsr;
443 *spr_val = vcpu->arch.tsr;
446 *spr_val = vcpu->arch.tcr;
450 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_CRITICAL];
453 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_MACHINE_CHECK];
456 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_DATA_STORAGE];
459 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_INST_STORAGE];
462 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_EXTERNAL];
465 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_ALIGNMENT];
468 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_PROGRAM];
471 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_FP_UNAVAIL];
474 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_SYSCALL];
477 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_AP_UNAVAIL];
480 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_DECREMENTER];
483 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_FIT];
486 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_WATCHDOG];
489 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_DTLB_MISS];
492 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_ITLB_MISS];
495 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_DEBUG];
498 *spr_val = vcpu->arch.mcsr;
502 *spr_val = vcpu->arch.epcr;