Lines Matching refs:arch
19 u64 msr = vcpu->arch.shregs.msr;
21 tfiar = vcpu->arch.regs.nip & ~0x3ull;
23 if (MSR_TM_SUSPENDED(vcpu->arch.shregs.msr))
29 vcpu->arch.tfiar = tfiar;
31 vcpu->arch.texasr = (vcpu->arch.texasr & 0x3ffffff) | texasr;
37 * instruction image is in vcpu->arch.emul_inst. If the guest was in
44 u32 instr = vcpu->arch.emul_inst;
45 u64 msr = vcpu->arch.shregs.msr;
56 vcpu->arch.regs.nip -= 4;
72 newmsr = vcpu->arch.shregs.srr1;
78 vcpu->arch.shregs.msr = newmsr;
79 vcpu->arch.cfar = vcpu->arch.regs.nip;
80 vcpu->arch.regs.nip = vcpu->arch.shregs.srr0;
84 if ((msr & MSR_PR) && (vcpu->arch.vcore->pcr & PCR_ARCH_206)) {
90 if (!(vcpu->arch.hfscr & HFSCR_EBB)) {
91 vcpu->arch.hfscr &= ~HFSCR_INTR_CAUSE;
92 vcpu->arch.hfscr |= (u64)FSCR_EBB_LG << 56;
93 vcpu->arch.trap = BOOK3S_INTERRUPT_H_FAC_UNAVAIL;
96 if ((msr & MSR_PR) && !(vcpu->arch.fscr & FSCR_EBB)) {
98 vcpu->arch.fscr &= ~FSCR_INTR_CAUSE;
99 vcpu->arch.fscr |= (u64)FSCR_EBB_LG << 56;
103 bescr = vcpu->arch.bescr;
110 vcpu->arch.bescr = bescr;
112 vcpu->arch.shregs.msr = msr;
113 vcpu->arch.cfar = vcpu->arch.regs.nip;
114 vcpu->arch.regs.nip = vcpu->arch.ebbrr;
128 vcpu->arch.shregs.msr = newmsr;
129 vcpu->arch.regs.nip += 4;
134 /* check for PR=1 and arch 2.06 bit set in PCR */
135 if ((msr & MSR_PR) && (vcpu->arch.vcore->pcr & PCR_ARCH_206)) {
141 if (!(vcpu->arch.hfscr & HFSCR_TM)) {
142 vcpu->arch.hfscr &= ~HFSCR_INTR_CAUSE;
143 vcpu->arch.hfscr |= (u64)FSCR_TM_LG << 56;
144 vcpu->arch.trap = BOOK3S_INTERRUPT_H_FAC_UNAVAIL;
149 vcpu->arch.fscr &= ~FSCR_INTR_CAUSE;
150 vcpu->arch.fscr |= (u64)FSCR_TM_LG << 56;
156 vcpu->arch.regs.ccr = (vcpu->arch.regs.ccr & 0x0fffffff) |
166 vcpu->arch.shregs.msr = msr;
167 vcpu->arch.regs.nip += 4;
173 if (!(vcpu->arch.hfscr & HFSCR_TM)) {
174 vcpu->arch.hfscr &= ~HFSCR_INTR_CAUSE;
175 vcpu->arch.hfscr |= (u64)FSCR_TM_LG << 56;
176 vcpu->arch.trap = BOOK3S_INTERRUPT_H_FAC_UNAVAIL;
181 vcpu->arch.fscr &= ~FSCR_INTR_CAUSE;
182 vcpu->arch.fscr |= (u64)FSCR_TM_LG << 56;
193 if (!(vcpu->arch.orig_texasr & TEXASR_FS)) {
203 vcpu->arch.regs.ccr = (vcpu->arch.regs.ccr & 0x0fffffff) |
205 vcpu->arch.shregs.msr &= ~MSR_TS_MASK;
206 vcpu->arch.regs.nip += 4;
213 if (!(vcpu->arch.hfscr & HFSCR_TM)) {
214 vcpu->arch.hfscr &= ~HFSCR_INTR_CAUSE;
215 vcpu->arch.hfscr |= (u64)FSCR_TM_LG << 56;
216 vcpu->arch.trap = BOOK3S_INTERRUPT_H_FAC_UNAVAIL;
221 vcpu->arch.fscr &= ~FSCR_INTR_CAUSE;
222 vcpu->arch.fscr |= (u64)FSCR_TM_LG << 56;
228 if (MSR_TM_ACTIVE(msr) || !(vcpu->arch.texasr & TEXASR_FS)) {
236 vcpu->arch.regs.ccr = (vcpu->arch.regs.ccr & 0x0fffffff) |
238 vcpu->arch.shregs.msr = msr | MSR_TS_S;
239 vcpu->arch.regs.nip += 4;