Lines Matching refs:shregs
45 hr->srr0 = vcpu->arch.shregs.srr0;
46 hr->srr1 = vcpu->arch.shregs.srr1;
47 hr->sprg[0] = vcpu->arch.shregs.sprg0;
48 hr->sprg[1] = vcpu->arch.shregs.sprg1;
49 hr->sprg[2] = vcpu->arch.shregs.sprg2;
50 hr->sprg[3] = vcpu->arch.shregs.sprg3;
113 hr->srr0 = vcpu->arch.shregs.srr0;
114 hr->srr1 = vcpu->arch.shregs.srr1;
115 hr->sprg[0] = vcpu->arch.shregs.sprg0;
116 hr->sprg[1] = vcpu->arch.shregs.sprg1;
117 hr->sprg[2] = vcpu->arch.shregs.sprg2;
118 hr->sprg[3] = vcpu->arch.shregs.sprg3;
155 vcpu->arch.shregs.srr0 = hr->srr0;
156 vcpu->arch.shregs.srr1 = hr->srr1;
157 vcpu->arch.shregs.sprg0 = hr->sprg[0];
158 vcpu->arch.shregs.sprg1 = hr->sprg[1];
159 vcpu->arch.shregs.sprg2 = hr->sprg[2];
160 vcpu->arch.shregs.sprg3 = hr->sprg[3];
183 vcpu->arch.shregs.srr0 = hr->srr0;
184 vcpu->arch.shregs.srr1 = hr->srr1;
185 vcpu->arch.shregs.sprg0 = hr->sprg[0];
186 vcpu->arch.shregs.sprg1 = hr->sprg[1];
187 vcpu->arch.shregs.sprg2 = hr->sprg[2];
188 vcpu->arch.shregs.sprg3 = hr->sprg[3];
303 if (MSR_TM_TRANSACTIONAL(vcpu->arch.shregs.msr))
333 if (MSR_TM_SUSPENDED(vcpu->arch.shregs.msr)) {
339 if (WARN_ON_ONCE(vcpu->arch.shregs.msr & MSR_TS_MASK))
354 vcpu->arch.regs.msr = vcpu->arch.shregs.msr;
370 vcpu->arch.shregs.msr = (vcpu->arch.regs.msr | MSR_ME) & ~MSR_HV;
383 l2_regs.msr = vcpu->arch.shregs.msr;
393 vcpu->arch.shregs.msr = saved_l1_regs.msr & ~MSR_TS_MASK;
396 vcpu->arch.shregs.msr |= MSR_TS_S;
1414 vcpu->arch.shregs.msr &= SRR1_MSR_BITS;
1415 vcpu->arch.shregs.msr |= flags;