Lines Matching refs:ull
379 #define MFC_CNTL_RESUME_DMA_QUEUE (0ull << 0)
380 #define MFC_CNTL_SUSPEND_DMA_QUEUE (1ull << 0)
381 #define MFC_CNTL_SUSPEND_DMA_QUEUE_MASK (1ull << 0)
382 #define MFC_CNTL_SUSPEND_MASK (1ull << 4)
383 #define MFC_CNTL_NORMAL_DMA_QUEUE_OPERATION (0ull << 8)
384 #define MFC_CNTL_SUSPEND_IN_PROGRESS (1ull << 8)
385 #define MFC_CNTL_SUSPEND_COMPLETE (3ull << 8)
386 #define MFC_CNTL_SUSPEND_DMA_STATUS_MASK (3ull << 8)
387 #define MFC_CNTL_DMA_QUEUES_EMPTY (1ull << 14)
388 #define MFC_CNTL_DMA_QUEUES_EMPTY_MASK (1ull << 14)
389 #define MFC_CNTL_PURGE_DMA_REQUEST (1ull << 15)
390 #define MFC_CNTL_PURGE_DMA_IN_PROGRESS (1ull << 24)
391 #define MFC_CNTL_PURGE_DMA_COMPLETE (3ull << 24)
392 #define MFC_CNTL_PURGE_DMA_STATUS_MASK (3ull << 24)
393 #define MFC_CNTL_RESTART_DMA_COMMAND (1ull << 32)
394 #define MFC_CNTL_DMA_COMMAND_REISSUE_PENDING (1ull << 32)
395 #define MFC_CNTL_DMA_COMMAND_REISSUE_STATUS_MASK (1ull << 32)
396 #define MFC_CNTL_MFC_PRIVILEGE_STATE (2ull << 33)
397 #define MFC_CNTL_MFC_PROBLEM_STATE (3ull << 33)
398 #define MFC_CNTL_MFC_KEY_PROTECTION_STATE_MASK (3ull << 33)
399 #define MFC_CNTL_DECREMENTER_HALTED (1ull << 35)
400 #define MFC_CNTL_DECREMENTER_RUNNING (1ull << 40)
401 #define MFC_CNTL_DECREMENTER_STATUS_MASK (1ull << 40)
579 #define MFC_LSACR_COMPARE_MASK ((~0ull) << 32)
580 #define MFC_LSACR_COMPARE_ADDR ((~0ull) >> 32)
585 #define MFC_LSCRR_QI_MASK ((~0ull) << MFC_LSCRR_QI_SHIFT)
630 #define SPU_ECC_CNTL_E (1ull << 0ull)
633 #define SPU_ECC_CNTL_S (1ull << 1ull)
636 #define SPU_ECC_CNTL_B (1ull << 2ull)
639 #define SPU_ECC_CNTL_I_SHIFT 3ull
640 #define SPU_ECC_CNTL_I_MASK (3ull << SPU_ECC_CNTL_I_SHIFT)
642 #define SPU_ECC_WRITE_CORRECTABLE (1ull << SPU_ECC_CNTL_I_SHIFT)
643 #define SPU_ECC_WRITE_UNCORRECTABLE (3ull << SPU_ECC_CNTL_I_SHIFT)
644 #define SPU_ECC_CNTL_D (1ull << 5ull)
648 #define SPU_ECC_CORRECTED_ERROR (1ull << 0ul)
649 #define SPU_ECC_UNCORRECTED_ERROR (1ull << 1ul)
650 #define SPU_ECC_SCRUB_COMPLETE (1ull << 2ul)
651 #define SPU_ECC_SCRUB_IN_PROGRESS (1ull << 3ul)
652 #define SPU_ECC_INSTRUCTION_ERROR (1ull << 4ul)
653 #define SPU_ECC_DATA_ERROR (1ull << 5ul)
654 #define SPU_ECC_DMA_ERROR (1ull << 6ul)
655 #define SPU_ECC_STATUS_CNT_MASK (256ull << 8)
658 #define SPU_ERR_ILLEGAL_INSTR (1ull << 0ul)
659 #define SPU_ERR_ILLEGAL_CHANNEL (1ull << 1ul)