Lines Matching refs:ull
408 #define H_CPU_CHAR_SPEC_BAR_ORI31 (1ull << 63) // IBM bit 0
409 #define H_CPU_CHAR_BCCTRL_SERIALISED (1ull << 62) // IBM bit 1
410 #define H_CPU_CHAR_L1D_FLUSH_ORI30 (1ull << 61) // IBM bit 2
411 #define H_CPU_CHAR_L1D_FLUSH_TRIG2 (1ull << 60) // IBM bit 3
412 #define H_CPU_CHAR_L1D_THREAD_PRIV (1ull << 59) // IBM bit 4
413 #define H_CPU_CHAR_BRANCH_HINTS_HONORED (1ull << 58) // IBM bit 5
414 #define H_CPU_CHAR_THREAD_RECONFIG_CTRL (1ull << 57) // IBM bit 6
415 #define H_CPU_CHAR_COUNT_CACHE_DISABLED (1ull << 56) // IBM bit 7
416 #define H_CPU_CHAR_BCCTR_FLUSH_ASSIST (1ull << 54) // IBM bit 9
417 #define H_CPU_CHAR_BCCTR_LINK_FLUSH_ASSIST (1ull << 52) // IBM bit 11
419 #define H_CPU_BEHAV_FAVOUR_SECURITY (1ull << 63) // IBM bit 0
420 #define H_CPU_BEHAV_L1D_FLUSH_PR (1ull << 62) // IBM bit 1
421 #define H_CPU_BEHAV_BNDS_CHK_SPEC_BAR (1ull << 61) // IBM bit 2
422 #define H_CPU_BEHAV_FAVOUR_SECURITY_H (1ull << 60) // IBM bit 3
423 #define H_CPU_BEHAV_FLUSH_COUNT_CACHE (1ull << 58) // IBM bit 5
424 #define H_CPU_BEHAV_FLUSH_LINK_STACK (1ull << 57) // IBM bit 6
425 #define H_CPU_BEHAV_NO_L1D_FLUSH_ENTRY (1ull << 56) // IBM bit 7
426 #define H_CPU_BEHAV_NO_L1D_FLUSH_UACCESS (1ull << 55) // IBM bit 8
427 #define H_CPU_BEHAV_NO_STF_BARRIER (1ull << 54) // IBM bit 9