Lines Matching refs:writeb
133 * readb/writeb to access them
167 writeb(cached_slave_mask, rm200_pic_slave + PIC_IMR);
169 writeb(cached_master_mask, rm200_pic_master + PIC_IMR);
182 writeb(cached_slave_mask, rm200_pic_slave + PIC_IMR);
184 writeb(cached_master_mask, rm200_pic_master + PIC_IMR);
194 writeb(0x0B, rm200_pic_master + PIC_CMD);
196 writeb(0x0A, rm200_pic_master + PIC_CMD);
199 writeb(0x0B, rm200_pic_slave + PIC_CMD); /* ISR register */
201 writeb(0x0A, rm200_pic_slave + PIC_CMD);
240 writeb(cached_slave_mask, rm200_pic_slave + PIC_IMR);
241 writeb(0x60+(irq & 7), rm200_pic_slave + PIC_CMD);
242 writeb(0x60+PIC_CASCADE_IR, rm200_pic_master + PIC_CMD);
245 writeb(cached_master_mask, rm200_pic_master + PIC_IMR);
246 writeb(0x60+irq, rm200_pic_master + PIC_CMD);
302 writeb(0x0C, rm200_pic_master + PIC_CMD); /* prepare for poll */
309 writeb(0x0C, rm200_pic_slave + PIC_CMD); /* prepare for poll */
321 writeb(0x0B, rm200_pic_master + PIC_ISR); /* ISR register */
337 writeb(0xff, rm200_pic_master + PIC_IMR);
338 writeb(0xff, rm200_pic_slave + PIC_IMR);
340 writeb(0x11, rm200_pic_master + PIC_CMD);
341 writeb(0, rm200_pic_master + PIC_IMR);
342 writeb(1U << PIC_CASCADE_IR, rm200_pic_master + PIC_IMR);
343 writeb(MASTER_ICW4_DEFAULT, rm200_pic_master + PIC_IMR);
344 writeb(0x11, rm200_pic_slave + PIC_CMD);
345 writeb(8, rm200_pic_slave + PIC_IMR);
346 writeb(PIC_CASCADE_IR, rm200_pic_slave + PIC_IMR);
347 writeb(SLAVE_ICW4_DEFAULT, rm200_pic_slave + PIC_IMR);
350 writeb(cached_master_mask, rm200_pic_master + PIC_IMR);
351 writeb(cached_slave_mask, rm200_pic_slave + PIC_IMR);