Lines Matching defs:rm200_pic_master
152 static __iomem u8 *rm200_pic_master;
169 writeb(cached_master_mask, rm200_pic_master + PIC_IMR);
184 writeb(cached_master_mask, rm200_pic_master + PIC_IMR);
194 writeb(0x0B, rm200_pic_master + PIC_CMD);
195 value = readb(rm200_pic_master + PIC_CMD) & irqmask;
196 writeb(0x0A, rm200_pic_master + PIC_CMD);
242 writeb(0x60+PIC_CASCADE_IR, rm200_pic_master + PIC_CMD);
244 readb(rm200_pic_master + PIC_IMR);
245 writeb(cached_master_mask, rm200_pic_master + PIC_IMR);
246 writeb(0x60+irq, rm200_pic_master + PIC_CMD);
302 writeb(0x0C, rm200_pic_master + PIC_CMD); /* prepare for poll */
303 irq = readb(rm200_pic_master + PIC_CMD) & 7;
321 writeb(0x0B, rm200_pic_master + PIC_ISR); /* ISR register */
322 if (~readb(rm200_pic_master + PIC_ISR) & 0x80)
337 writeb(0xff, rm200_pic_master + PIC_IMR);
340 writeb(0x11, rm200_pic_master + PIC_CMD);
341 writeb(0, rm200_pic_master + PIC_IMR);
342 writeb(1U << PIC_CASCADE_IR, rm200_pic_master + PIC_IMR);
343 writeb(MASTER_ICW4_DEFAULT, rm200_pic_master + PIC_IMR);
350 writeb(cached_master_mask, rm200_pic_master + PIC_IMR);
391 rm200_pic_master = ioremap(0x16000020, 4);
392 if (!rm200_pic_master)
396 iounmap(rm200_pic_master);