Lines Matching refs:set
24 .set mips32
28 .set mips0
54 /* set up CPU1 CBR; move BASE to 0xa000_0000 */
57 /* set up relocation vector address based on thread ID */
82 .set push
83 .set noat
126 .set arch=r4000
173 /* set up CP0 STATUS; enable FPU */
178 /* set local CP0 CONFIG to make kseg0 cacheable, write-back */
210 /* set exception vector base */
224 /* use temporary stack to set up upper memory TLB */
248 .set pop