Lines Matching defs:ref_div
148 u32 ref_div;
167 ref_div = 1;
182 ref_div = t;
205 ref_div * out_div * cpu_div);
207 ref_div * out_div * ddr_div);
209 ref_div * out_div * ahb_div);
212 static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac,
220 do_div(t, ref_div);
225 do_div(t, ref_div * frac);
238 u32 pll, out_div, ref_div, nint, nfrac, frac, clk_ctrl, postdiv;
261 ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) &
268 ref_div = (pll >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
277 cpu_pll = ar934x_get_pll_freq(ref_rate, ref_div, nint,
288 ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) &
295 ref_div = (pll >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
304 ddr_pll = ar934x_get_pll_freq(ref_rate, ref_div, nint,
356 u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
371 ref_div = (pll >> QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
378 cpu_pll = nint * ref_rate / ref_div;
379 cpu_pll += frac * (ref_rate >> 6) / ref_div;
385 ref_div = (pll >> QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
392 ddr_pll = nint * ref_rate / ref_div;
393 ddr_pll += frac * (ref_rate >> 6) / (ref_div << 4);
439 u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
454 ref_div = (pll >> QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
461 cpu_pll = nint * ref_rate / ref_div;
462 cpu_pll += frac * ref_rate / (ref_div * (1 << 6));
468 ref_div = (pll >> QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
475 ddr_pll = nint * ref_rate / ref_div;
476 ddr_pll += frac * ref_rate / (ref_div * (1 << 10));
522 u32 pll, out_div, ref_div, nint, hfrac, lfrac, clk_ctrl, postdiv;
547 ref_div = (pll >> QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
558 cpu_pll = nint * ref_rate / ref_div;
559 cpu_pll += (lfrac * ref_rate) / ((ref_div * 25) << 13);
560 cpu_pll += (hfrac >> 13) * ref_rate / ref_div;
566 ref_div = (pll >> QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
576 ddr_pll = nint * ref_rate / ref_div;
577 ddr_pll += (lfrac * ref_rate) / ((ref_div * 25) << 13);
578 ddr_pll += (hfrac >> 13) * ref_rate / ref_div;